Protective Layer for Stable Ohmic Contacts in Wide Bandgap Semiconductors

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Solution Overview

Problem

High-temperature annealing required for lattice damage repair in semiconductor materials can exceed the dissociation temperature of certain materials, making it challenging to form stable implanted regions for ohmic contacts, especially in wide bandgap semiconductors like silicon carbide and Group III nitrides.

Innovation Solution

A method involving the formation of a protective layer, such as silicon nitride, on the semiconductor layer to withstand high temperatures during ion implantation and annealing, allowing for the creation of implanted regions with controlled dopant distribution and activation, enabling ohmic contact formation without damaging the underlying material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-temperature annealing is performed to repair lattice damage and activate dopants, then the implanted region stability and ohmic contact quality improve, but the semiconductor material may dissociate or degrade at temperatures above its dissociation point

Engineering Contradiction:
Improveimplanted region stabilityVSAvoidmaterial composition stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

A protective capping layer is introduced as an intermediary between the ion implantation system and the semiconductor material. This layer withstands high temperatures during annealing without reacting with the underlying semiconductor, enabling lattice damage repair and dopant activation at temperatures that would otherwise cause material dissociation. The capping layer serves as a thermal buffer and chemical barrier, mediating the conflict between high-temperature processing requirements and material stability constraints.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective capping layer is formed on the semiconductor material before ion implantation and subsequent high-temperature annealing. This preliminary protective action ensures that when high-temperature annealing is performed to repair lattice damage and activate dopants, the semiconductor material is already shielded from thermal dissociation and chemical degradation, allowing the annealing process to proceed without compromising material composition stability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If ion implantation is performed to create doped regions for ohmic contacts, then the electrical conductivity and contact quality improve, but lattice damage and structural defects are introduced into the semiconductor material

Engineering Contradiction:
Improveohmic contact qualityVSAvoidlattice structure integrity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The high-temperature annealing process, which could potentially cause material degradation, is converted into a beneficial treatment that repairs lattice damage caused by ion implantation. By controlling the annealing conditions and using a protective capping layer, the harmful lattice defects and broken bonds created during implantation are transformed into a restored crystal structure with activated dopants, thereby improving both lattice integrity and electrical conductivity simultaneously.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The physical and chemical state of the semiconductor material is changed through controlled thermal annealing. By adjusting temperature, time, and atmosphere parameters, the material transitions from a damaged, non-conductive state (immediately after implantation) to a repaired, highly conductive state with activated dopants. This parameter change enables the conversion of lattice damage into structural restoration while maintaining the implanted dopant distribution.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a protective capping layer is added to withstand high temperatures during annealing, then material degradation is prevented, but the device structure and fabrication complexity increase

Engineering Contradiction:
Improvematerial stability during processingVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective capping layer is designed to perform multiple functions: (1) protecting the semiconductor material from thermal dissociation during high-temperature annealing, (2) serving as a barrier against contaminant ingress, (3) potentially acting as a dopant source or blocking layer depending on composition, and (4) providing mechanical support during subsequent processing steps. This multi-functionality reduces the need for additional separate protective measures, thereby limiting the increase in fabrication complexity while maximizing material protection benefits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the formation of stable implanted regions with precise dopant distribution, facilitating efficient ohmic contacts and reducing material degradation, thereby improving the performance and reliability of semiconductor devices.

Implementation Method 1

Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

The material of the capping layer may be stable at high temperatures, and may not react with the underlying implanted semiconductor layer

Methodology Applied
Scientific EffectThermal stability:

Data Source

PatentUS9984881B2Methods of fabricating semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
Publication Date: 2018.05.29 WOLFSPEED INC
  • US9984881B2 patent drawing
  • US9984881B2 patent drawing
  • US9984881B2 patent drawing

AI summary

Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.