Semiconductor Package Protective Layer Stack for Low-Warpage Reliability
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Solution Overview
Problem
Semiconductor packages face warpage issues due to differences in coefficients of thermal expansion between various materials used, affecting their reliability and yield.
Innovation Solution
The use of a semiconductor package design featuring a substrate with a first and second upper protective layer, where the second upper protective layer has a lower coefficient of thermal expansion and higher tensile strength than the first, strategically positioned to improve warpage properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single protective layer is used on the substrate, then the structure is simple and manufacturing is easier, but warpage occurs due to mismatch in coefficients of thermal expansion between different materials
Solution Approach 1:
The protective layer is divided into two distinct layers: a first protective layer (solder resist layer) and a second protective layer (upper protective layer). This segmentation allows each layer to serve different functions - the first layer provides basic protection and solder resistance, while the second layer specifically addresses warpage control through its lower coefficient of thermal expansion, matching the substrate's CTE more closely.
Solution Approach 2:
The patent employs composite material structure with two protective layers having different material properties. The first protective layer uses a material with higher CTE (e.g., solder resist material), while the second protective layer uses a material with lower CTE closer to the substrate. This composite structure creates a gradient that reduces overall thermal expansion mismatch and minimizes warpage.
2Adaptability or versatility
If materials with different coefficients of thermal expansion are used in the package, then functional requirements are met, but warpage is caused due to thermal expansion mismatch
Solution Approach 1:
The second protective layer is positioned specifically at the edges and corners of the substrate where warpage tends to occur most. This layer has locally optimized material properties (lower CTE) to counteract the thermal expansion forces at these critical locations, providing localized warpage control without affecting the overall package functionality.
Solution Approach 2:
The patent deliberately selects materials for the second protective layer with a coefficient of thermal expansion that is lower than the first protective layer and closer to the substrate's CTE. This strategic material selection creates a thermal expansion gradient that compensates for the expansion forces generated by other package components during temperature cycling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively minimizes warpage and enhances the reliability and yield of semiconductor packages by utilizing insulating materials with specific thermal expansion and tensile strength properties, improving the package's structural integrity.
Implementation Method 1
The second upper protective layer may include a second insulating material having a coefficient of thermal expansion (CTE) lower than a CTE of the first insulating material
Implementation Method 2
The second upper protective layer may include a second insulating material having a coefficient of thermal expansion (CTE) lower than a CTE of the first insulating material and a tensile strength higher than a tensile strength of the first insulating material
Data Source
AI summary
A semiconductor package includes a substrate having a lower surface and an opposite upper surface, an insulating layer, and a wiring layer on the insulating layer. A first upper protective layer is on the upper surface and includes first openings. A second upper protective layer is on the first upper protective layer. A semiconductor chip is on the first upper protective layer and includes connection pads electrically connected to the wiring layer through the first openings. An encapsulant seals at least a portion of the semiconductor chip, and the second upper protective layer. The first upper protective layer includes a first insulating material. The second upper protective layer includes a second insulating material having a coefficient of thermal expansion lower than that of the first insulating material and a tensile strength higher than that of the first insulating material.