Protective Layer Suppresses Divots in STI Junction Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Shallow trench isolation (STI) regions in integrated circuits suffer from non-uniform silicide formation due to divot formation during wet etching, leading to elevated junction leakage and contact resistance variations, which negatively impact transistor performance.
Innovation Solution
A protective layer with a lower etch rate than SiO2 is deposited between STI regions and semiconductor active regions to suppress divot formation, ensuring uniform silicide formation across the semiconductor active region. This layer can be an oxide, oxy-nitride, carbide, or metal oxide, and is designed to withstand wet etching processes while preventing divot creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wet etching is used to form STI regions, then isolation between adjacent semiconductor devices is achieved, but divot formation occurs leading to non-uniform silicide formation and elevated junction leakage
Solution Approach 1:
A protective layer is introduced as an intermediary between the wet etching process and the oxide liner. This protective layer selectively resists etching while allowing the etch to proceed in other areas, thereby preventing divot formation at the interface between the STI region and semiconductor active region without compromising the isolation function
Solution Approach 2:
The protective layer is applied beforehand to preemptively counteract the harmful etching effect. By being in place before the wet etching process, it proactively prevents the divot formation that would otherwise occur during etching, thereby maintaining silicide uniformity while still achieving isolation
2Reliability
If oxide liner is used between dielectric and semiconductor structure, then electrical isolation is provided, but divot formation occurs during wet etching of dielectric material
Solution Approach 1:
The protective layer serves as a mediator that shields the oxide liner from direct exposure to the wet etching chemistry. It allows the dielectric material to be etched away for isolation purposes while the protective layer remains intact to prevent the etch from attacking the oxide liner and creating divots
Solution Approach 2:
The protective layer is designed to be self-removable or self-adjusting. After serving its protective function during wet etching, it can be selectively removed or integrated into the subsequent processing steps without requiring additional complex process steps, thereby maintaining oxide liner integrity while enabling effective dielectric etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in divot-free STI regions, leading to improved silicide thickness uniformity and reduced junction leakage, enhancing transistor performance by minimizing contact resistance variations and power consumption.
Implementation Method 1
A protective layer with a lower etch rate than SiO2 is deposited between STI regions and semiconductor active regions to suppress divot formation, ensuring uniform silicide formation across the semiconductor active region.
Data Source
AI summary
The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.