Source/Drain Contact Openings With Protective Layer Against FinFET Shorting

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, challenges arise in maintaining integration density and preventing shorting of adjacent source/drain regions during the manufacturing process, particularly in the formation of contact openings in FinFETs.

Innovation Solution

The process involves initially forming contact openings to a smaller width and then expanding them to a larger width using a controlled etching process, and applying a protective layer to prevent shorting and protect surrounding features during the formation of metal-semiconductor alloy regions on the source/drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact openings are formed directly to the required width, then manufacturing process is simpler, but adjacent source/drain regions may short

Engineering Contradiction:
Improveprevention of shortingVSAvoidcontact formation process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact opening formation process is divided into two separate etching steps: first forming initial contact openings through the interlayer dielectric, then forming contact holes through the mandrel and into the source/drain regions. This segmentation allows each step to be optimized independently, preventing shorting while maintaining process control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A mandrel structure is formed beforehand and used as a template to guide the formation of contact holes. The mandrel is positioned between adjacent source/drain regions and serves as a physical barrier during etching, preventing the etch from creating direct pathways between adjacent regions. This preliminary structure enables reliable contact formation without risk of shorting.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision becomes harder to maintain

Engineering Contradiction:
Improveintegration densityVSAvoidcontact opening dimensions
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The mandrel structure serves multiple functions automatically: it defines the contact hole position, controls the contact hole width, and prevents etching into adjacent source/drain regions. The self-aligned nature of the mandrel eliminates the need for separate alignment steps, maintaining precision even as feature sizes are reduced to increase integration density.

Inventive Principle:
Principle #25Self-service

3Reliability

If protective layer is applied during metal-semiconductor alloy formation, then surrounding features are protected from etching, but process steps increase

Engineering Contradiction:
Improveprotection of gate maskVSAvoidnumber of process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The mandrel structure serves multiple purposes throughout the process: it acts as a spacer during contact opening formation, provides a template for contact hole positioning, and serves as a protective barrier during metal-semiconductor alloy formation. By making the mandrel multi-functional, additional protective measures are unnecessary, avoiding increases in process complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves manufacturing yield by avoiding shorting of adjacent source/drain regions and enhances device performance by ensuring accurate contact formation with highly doped regions of the epitaxial source/drain regions.

Implementation Method 1

the protective layer covering the gate mask during the cleaning process

Methodology Applied
Scientific EffectPhysical barrier protection:

Implementation Method 2

annealing the metal to form a metal-semiconductor alloy region on the source/drain region

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

etching an opening through the protective layer, the opening exposing the source/drain region

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11798943B2Transistor source/drain contacts and methods of forming the same
Publication Date: 2023.10.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11798943B2 patent drawing
  • US11798943B2 patent drawing
  • US11798943B2 patent drawing

AI summary

In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.