Protective Wafer Grooving for Low-k Damage During Thinning
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Solution Overview
Problem
The challenge in wafer thinning is the vulnerability of low-k dielectric materials to structural and chemical damages during processing, which affects the performance and reliability of semiconductor devices.
Innovation Solution
A protective wafer grooving structure is implemented, involving the formation of an inter-wafer moat trench and a protective material layer to shield the low-k dielectric materials, along with blade-trimming and additional thinning processes to prevent mechanical and chemical damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer thinning is performed to enable vertical stacking and bonding, then chip density and operational speed are improved, but low-k dielectric materials suffer structural and chemical damages
Solution Approach 1:
A protective material layer is formed over the low-k dielectric material before the thinning process begins. This preliminary protective action shields the dielectric material from structural and chemical damages that occur during subsequent thinning operations, allowing the wafer to be thinned while maintaining dielectric integrity.
Solution Approach 2:
The protective material layer acts as an intermediary between the thinning process and the low-k dielectric material. This intermediate layer absorbs mechanical stress and prevents direct contact between thinning tools and the sensitive dielectric material, thereby preventing both structural and chemical damages while enabling the thinning necessary for high-density stacking.
2Productivity
If aggressive thinning processes are used to reduce wafer thickness, then manufacturing efficiency is improved, but mechanical stress and contamination increase
Solution Approach 1:
The protective material layer is deposited beforehand to cushion and absorb mechanical stress during the thinning process. This prior cushioning allows aggressive thinning operations to proceed with high efficiency while the protective layer prevents excessive mechanical stress from reaching the underlying dielectric materials and semiconductor structures.
3Reliability
If protective material layer is added to shield dielectric materials, then dielectric protection is improved, but process complexity increases
Solution Approach 1:
The protective material layer is applied selectively to specific regions where low-k dielectric materials are located, rather than uniformly across the entire wafer. This localized protection approach maintains dielectric material integrity while minimizing the addition of process steps and reducing overall process complexity.
Data Source
AI summary
A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.