Protocol Checking Logic Circuit for Memory Reliability
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Solution Overview
Problem
Traditional memory systems are susceptible to propagation of erroneous commands due to simple parity schemes, leading to difficulty in recovering memory devices from unknown or undefined states during catastrophic failures of the host memory controller.
Innovation Solution
A buffer integrated circuit device with a Protocol and Parity Checking Block that processes command and address bus information, blocking erroneous commands and maintaining memory devices in a known state by ensuring compliance with defined memory access protocols, using a programmable table with timing parameters and a command history table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple parity schemes are used for command validation, then device complexity is reduced, but reliability deteriorates due to propagation of erroneous commands during catastrophic failures
Solution Approach 1:
The protocol checking block segments the command validation process into multiple independent stages: parity checking, protocol compliance checking, and command history verification. Each stage operates independently to validate different aspects of the command, allowing comprehensive validation without requiring a single complex validation circuit.
Solution Approach 2:
The system performs preliminary protocol compliance checking and command history verification before allowing commands to execute. The command history table pre-stores valid command sequences and timing parameters, enabling the system to validate commands against known good sequences before execution, preventing erroneous commands from propagating.
2Reliability
If protocol compliance checking is implemented, then reliability is improved by blocking erroneous commands, but device complexity increases due to additional checking circuits
Solution Approach 1:
The protocol compliance checking function is merged with the existing parity checking block. Both parity checking and protocol compliance checking are performed within the same buffer integrated circuit device, sharing common resources such as the command history table and timing parameter storage, thereby reducing overall system complexity.
Solution Approach 2:
The command history table serves as an intermediary structure that stores pre-defined valid command sequences and timing parameters. Instead of implementing complex real-time protocol validation logic, the system uses this intermediary table to compare against incoming commands, simplifying the checking circuitry while maintaining comprehensive protocol validation.
3Reliability
If command history table is used for protocol validation, then reliability is improved, but loss of time occurs due to additional validation processing
Solution Approach 1:
Valid command sequences, timing parameters, and state transitions are pre-calculated and stored in the command history table during system initialization or manufacturing. This preliminary action eliminates the need for complex real-time calculations, allowing the protocol checking block to perform rapid table-lookup-based validation that adds minimal processing time.
Solution Approach 2:
Instead of implementing complex protocol validation logic that would require extensive processing, the system creates simplified copies of valid command sequences and stores them in the command history table. The validation process then uses simple comparison operations against these copied sequences, significantly reducing validation time while maintaining comprehensive error detection.
4Productivity
If buffer integrated circuit device is used to reduce loading, then productivity is improved, but device complexity increases due to protocol checking block
Solution Approach 1:
The buffer integrated circuit device is designed with multi-functionality, serving both as a load-reducing buffer and as a protocol compliance checking unit. The same device that buffers commands and addresses also performs parity checking, protocol validation, and command history verification, eliminating the need for separate validation circuits and reducing overall system complexity.
Solution Approach 2:
The protocol checking block is merged into the buffer integrated circuit device structure. The parity checking circuit, command history table, and protocol validation logic are integrated within the same device that performs buffering operations, allowing both functions to share resources and operate efficiently without adding separate complex validation subsystems.
Data Source
AI summary
A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.