Protocol Verification Buffering for Emulation Data Latency

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Solution Overview

Problem

Existing hardware-based emulation platforms generate immense amounts of data during circuit design verification, which can lead to data loss, corruption, or inefficiencies in communication protocol testing due to the inability of computing systems to handle these data transfers effectively.

Innovation Solution

Implementing a database system with a memory layer and local storage layer to buffer and aggregate response data based on communication speed and storage capacity, using buffering criteria to optimize data transfer to a database system for efficient storage and analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If response data is stored directly in local storage layer, then storage capacity is sufficient, but memory access latency increases

Engineering Contradiction:
Improvestorage capacityVSAvoidmemory access latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The storage system is segmented into two distinct layers: a memory layer for high-speed access and a local storage layer for large-capacity storage. This segmentation allows the system to utilize the strengths of each layer independently, with the memory layer handling time-critical operations and the local storage layer providing bulk storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory layer acts as an intermediary between the hardware-based emulation platform and the local storage layer. It buffers response data temporarily, providing a high-speed access point that mediates between the fast emulation platform and the slower but larger-capacity local storage, thereby reducing overall access latency while maintaining sufficient storage capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data is transferred directly from hardware-based emulation platform to database system, then data integrity is maintained, but communication efficiency decreases

Engineering Contradiction:
Improvedata integrityVSAvoidcommunication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary buffering of response data in the memory layer before transferring it to the database system. This preliminary action organizes and prepares data in a high-speed buffer, allowing for more efficient batch transfers to the database system while maintaining data integrity through controlled data flow management.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory layer and verification system together form an intermediary layer between the hardware-based emulation platform and the database system. This intermediary buffers, aggregates, and manages data transfers, improving communication efficiency by reducing direct transfer overhead while maintaining data integrity through structured data handling protocols.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If aggregation of response data is performed frequently, then communication overhead to database system is reduced, but memory buffering complexity increases

Engineering Contradiction:
Improvecommunication overhead reductionVSAvoidmemory buffering complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The verification system performs periodic aggregation of response data from the memory layer to the local storage layer and database system. Instead of continuous or overly frequent aggregation, the system uses periodic batch transfers based on buffering criteria, which reduces communication overhead while avoiding the complexity of continuous real-time aggregation management.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system aggregates only the necessary portion of buffered data that meets specific criteria (such as buffer threshold or time-based conditions) rather than aggregating all data continuously. This partial aggregation approach reduces communication overhead for database writes while avoiding the complexity of managing full continuous aggregation of all response data.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12505275B2Communication protocols design verification through database systems for hardware-based emulation platforms
Publication Date: 2025.12.23 SIEMENS INDUSTRY SOFTWARE INC
  • US12505275B2 patent drawing
  • US12505275B2 patent drawing
  • US12505275B2 patent drawing

AI summary

A system may include a hardware-based emulation platform configured to emulate operation of a design-under-test (“DUT”), a database system, and a verification system. The verification system may include a storage system which may include a memory layer and a local storage layer, where the memory layer has a lower memory access latency than the local storage layer. The verification system may also include a design verification engine configured to send test data to the hardware-based emulation platform; buffer response data received from the DUT into the memory layer and the local storage layer; determine to aggregate the response data stored in both the memory layer and local storage layer into a write transaction according to buffering criteria, and issue the write transaction to the database system to store the aggregated response data in the database system.