Time-Shared Protograph LDPC Decoding With Fewer Check-Node Processors
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Solution Overview
Problem
Previous protograph decoders based on LDPC architectures do not scale down in size and throughput due to the requirement of separate check-node processors for each check node, leading to inefficiencies in hardware usage and increased costs.
Innovation Solution
Implementing a time-sharing method for check node processors, where check nodes of the same degree can be implemented using a single processor by time division multiplexing different edge connection input values, allowing a single check node processor to handle multiple check nodes with varying degrees, and replacing multiple shift registers with a single RAM for cost-effective storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate check-node processors are used for each check node, then decoding accuracy is maintained, but hardware size and cost increase
Solution Approach 1:
A single check-node processor is designed to handle multiple check nodes by dynamically reconfiguring its edge connections through time-division multiplexing. The processor can be programmed to implement different check nodes of the same degree by changing the active edges, making it a universal component that replaces multiple dedicated processors.
Solution Approach 2:
The check-node processor employs dynamic edge activation where edges are selectively activated or deactivated based on which check node is currently being processed. This dynamic reconfiguration allows the same hardware to adapt to different check node requirements, enabling one processor to perform the work of multiple processors.
2Productivity
If separate check-node processors are used for each check node, then processing capacity is sufficient, but throughput efficiency decreases
Solution Approach 1:
While one check node is being processed, other check nodes are being prepared in parallel using the same processor. The time-division multiplexing allows continuous utilization of the processor by switching between different check nodes without idle time, maintaining high processing capacity while improving overall throughput efficiency.
Solution Approach 2:
The system pre-organizes check nodes by degree and prepares their edge connections in advance. Before a check node is processed, its corresponding edges are activated and data is prepared, allowing the processor to immediately begin work without setup delays, thus maintaining processing capacity while reducing transition time.
3Reliability
If multiple shift registers are used for storage, then data availability is ensured, but hardware cost increases
Solution Approach 1:
Multiple separate shift registers are merged into a single shared memory structure that serves all check nodes. The memory is organized to store edge data for multiple check nodes, and a single memory interface retrieves the required data for the currently active check node, eliminating the need for multiple redundant shift registers.
Solution Approach 2:
A single memory interface acts as an intermediary between the shared memory and the check-node processor. This interface manages data retrieval for different check nodes by selecting the appropriate edges based on the current check node being processed, ensuring data availability while reducing hardware cost by eliminating multiple interfaces.
Data Source
AI summary
An LDPC decoder includes a check node processor. The check node processor is configured to implement an n-degree check node, where n is a predetermined number. The degree of a check node is the number of edges coupled to the check node. The LDPC decoder also includes a plurality of n time division multiplexers coupled to the check node processor to couple different edge connection input values to the check node processor at different times so as to allow the check node processor to be time division multiplexed for use in implementing different check nodes with the same check node processor. Each of the multiplexers is configured to provide no more than one edge connection input value to the check node processor at any given time. Each edge connection is used to implement an edge into a check node.