CMOS-Compatible Protonic Resistive Memory Device

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Solution Overview

Problem

Current resistive memory technologies for deep learning applications face challenges with asymmetric modulation dynamics, limited programmable states, and incompatibility with CMOS processing, which hinders scaling and integration.

Innovation Solution

A 3-terminal protonic nonvolatile memory device is developed using a metal oxide channel and Si-based layers as a protonic electrolyte or reservoir, where proton conductivity is tuned by controlling the concentration of intercalated protons through electrical pulses, utilizing CMOS-compatible materials and processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If battery-like systems with ionic species insertion are used to achieve high number of programmable states, then the number of programmable states is improved, but compatibility with CMOS processing deteriorates

Engineering Contradiction:
Improvenumber of programmable statesVSAvoidCMOS processing compatibility
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent changes the ionic species from conventional Li+ or Mg+ to protons (H+), enabling the use of silicon-based electrolytes that are CMOS-compatible. This parameter change in the type of ionic species allows the device to maintain high programmable states while being compatible with standard CMOS fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures including silicon-based electrolyte layers combined with metal oxide active layers. These composite materials enable both the desired functionality (high number of programmable states through proton intercalation) and compatibility with CMOS processing techniques.

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If conventional resistive memory technologies are used, then manufacturing simplicity is maintained, but the number of programmable states and modulation symmetry are limited

Engineering Contradiction:
Improvenumber of programmable statesVSAvoidmodulation dynamics symmetry
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent replaces conventional electrical resistance modulation mechanisms with an electrochemical mechanism based on proton intercalation. This substitution enables symmetric and fast modulation characteristics while achieving a high number of programmable nonvolatile states, overcoming the limitations of conventional resistive memory.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent utilizes phase transition-like behavior in the metal oxide active layer during proton intercalation and deintercalation. This mechanism enables reversible and symmetric modulation between different conductance states, achieving both high programmable states and symmetric modulation dynamics.

Inventive Principle:
Principle #36Phase transitions

3Speed

If proton intercalation mechanisms are implemented, then symmetric and fast modulation characteristics are achieved, but material compatibility with CMOS processing deteriorates

Engineering Contradiction:
Improvemodulation speedVSAvoidCMOS processing compatibility
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent changes the electrolyte material parameter from conventional non-silicon-based materials to silicon-based materials, enabling CMOS compatibility. This parameter change maintains the proton intercalation mechanism's symmetric and fast modulation characteristics while allowing fabrication using standard CMOS processing techniques.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables high-yield, high-performance protonic resistive memory for analog computing applications, addressing the limitations of existing technologies by providing scalable and efficient protonic resistive devices compatible with CMOS manufacturing.

Implementation Method 1

The conductivity of the metal oxide layer is tuned by controlling the concentration of intercalated protons (i.e. hydrogen ions or H+). Protons are forced into/out of the metal oxide layer by application of electrical pulses to a gate element.

Methodology Applied
Scientific EffectProton intercalation:

Implementation Method 2

a proton containing electrolyte-reservoir layer disposed on the active layer

Methodology Applied
Scientific EffectIonic conduction: Conduction (electrical)

Data Source

PatentUS11462683B2CMOS-compatible protonic resistive devices
Publication Date: 2022.10.04 MASSACHUSETTS INST OF TECH
  • US11462683B2 patent drawing
  • US11462683B2 patent drawing
  • US11462683B2 patent drawing

AI summary

Described are CMOS-compatible protonic resistive devices (e.g., processing elements and/or memory elements). In embodiments, a protonic resistive memory can be formed from a proton-sensitive metal oxide channel where the concentration of protons intercalated inside the layer is controlled to modulate its conductivity. The protons can initially be supplied to the material stack by an implantation method. Irradiation techniques can be implemented to increase the concentration and conductivity of protons inside the materials. Some designs can put the active layer and reservoir in direct contact, creating an electrolyte-free device. Designs provide scalable solutions for full-scale Si-integration.