Prototype Parameterized Cells for Early DRC and LVS Validation
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Solution Overview
Problem
The process of generating parameterized cells (PCELLs) for integrated circuit (IC) designs is time-consuming and prone to delays due to the complexity of configurations, leading to issues in downstream design processes like design rule checking (DRC) and layout versus schematic (LVS) checking, necessitating reverse engineering without source code access.
Innovation Solution
A system and method for developing a prototype parameterized cell (P-PCELL) using graphic design system (GDS) files and a mapping file, optionally with machine learning models, followed by evaluation and feedback-based updates to address DRC errors and irregularities before inclusion in a PCELL library.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional PCELL generation methods are used, then PCELLs can be created for IC designs, but the process is time-consuming and delays detection of problems in downstream design processes
Solution Approach 1:
The patent applies preliminary action by performing DRC and LVS checks during the PCELL generation phase itself, rather than waiting for downstream design processes. The system generates test patterns and performs validation checks before the PCELL is finalized, enabling early detection of configuration problems and eliminating the need for time-consuming reverse engineering later.
2Reliability
If comprehensive PCELL configurations are evaluated, then problems can be detected early, but the exponential complexity of all possible configurations makes reverse engineering extremely difficult
Solution Approach 1:
The patent uses copying by creating simplified test patterns that replicate the essential characteristics of complex PCELL configurations. Instead of evaluating all possible complex configurations directly, the system generates representative test cases that can be processed efficiently, maintaining validation effectiveness while reducing computational complexity.
3Productivity
If PCELL developers finalize code without early evaluation, then development can proceed, but problems are detected late requiring modification without source code access
Solution Approach 1:
The patent implements feedback by continuously evaluating PCELL configurations during the generation process through automated DRC and LVS checks. The system provides immediate feedback on configuration correctness, allowing developers to modify the source code while it is still accessible, rather than attempting reverse engineering after finalization.
Data Source
AI summary
Disclosed are a system, method, and computer program product for developing and evaluating a prototype parameterized cell (P-PCELL) for a specific integrated circuit component. The P-PCELL is developed using multiple graphic design system (GDS) files for the component and a mapping file. Optionally, P-PCELL development is performed using a first machine learning model. Optionally, the P-PCELL is also evaluated based on test feedback acquired through user-testing including, for example, design rule checking (DRC) errors. Updates (e.g., design manual and/or parameter range updates) can be developed given the DRC errors. Optionally, development of the updates is performed using a second machine learning model. P-PCELL evaluation can further include determining P-PCELL code functionality, de-bugging the P-PCELL code, detecting any irregularities in the P-PCELL (e.g., based on a comparison of user-customized configurations with specifications and the GDS files) and correcting such irregularities.