Protruded Conductive Pillars for Fine Pitch WLCSP Stacking
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Solution Overview
Problem
Conventional wafer level chip scale packages (WLCSP) face challenges in achieving fine interconnect pitch and vertical package integration, making it difficult to stack semiconductor devices without increasing package height or compromising electrical connectivity.
Innovation Solution
The development of a semiconductor device with protruded conductive pillars that provide z-direction interconnects, allowing for finer pitch interconnections and increased joint strength when stacking, while also reducing the overall package profile through the use of conductive vias and layers within an encapsulant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional WLCSP interconnect structures are used, then the package can be manufactured with standard processes, but the interconnect pitch cannot be made fine and vertical stacking is difficult
Solution Approach 1:
The patent transitions from planar interconnect structures to three-dimensional protruded conductive pillars extending through the encapsulant. This dimensional change enables fine pitch interconnections by utilizing vertical space, allowing multiple interconnect levels without increasing lateral footprint, thus facilitating vertical stacking while maintaining fine pitch requirements
Solution Approach 2:
The conductive pillars are nested within the encapsulant structure, with the encapsulant providing mechanical support and protection while the pillars provide electrical interconnection. This nested configuration allows the interconnect structure to be integrated within the package volume without increasing external dimensions, enabling finer pitch and easier stacking
2Strength
If solder bump or solder ball interconnects are used, then electrical connectivity is achieved, but joint strength is insufficient and package profile increases
Solution Approach 1:
The patent changes the physical parameters of the interconnect structure by using protruded conductive pillars with controlled height, width, and material composition. These parameter changes enable increased joint strength through larger bonding area and optimized mechanical properties, while the controlled dimensions reduce the overall package profile compared to traditional solder bumps
Solution Approach 2:
The interconnect structure uses composite construction with conductive material pillars embedded in encapsulant material. This composite approach combines the electrical conductivity of metal pillars with the mechanical support and insulation of the encapsulant, achieving both high joint strength and compact package profile
Data Source
AI summary
A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars.