Protruding Floating Gate Flash Memory Fabrication
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Solution Overview
Problem
Flash memory cells are bulky due to complex geometries of multiple gate layers, limiting their integration into compact devices, and the gate coupling ratio between the floating and control gates affects operating voltage and speed, making it difficult to decrease floating gate-floating gate capacitance and increase the overlapped area between the control and floating gates.
Innovation Solution
A method is developed to fabricate a protruding floating gate in flash memory devices by forming a substrate with isolation structures, depositing conductive layers using PVD or CVD, and employing chemical-mechanical polishing and lithography processes to increase the overlapped area between the control and floating gates, thereby enhancing the gate coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional stacked gate structure is used, then fabrication process is simpler, but gate coupling ratio is low and device area is large
Solution Approach 1:
The patent transitions from a conventional planar stacked gate structure to a three-dimensional protruding floating gate structure. The floating gate extends vertically and horizontally to overlap with the control gate in multiple dimensions, increasing the coupled area without significantly complicating the fabrication process. This dimensional change allows achieving higher gate coupling ratio while maintaining fabrication simplicity.
Solution Approach 2:
The floating gate is divided into multiple segments or regions with different heights and positions. By segmenting the floating gate structure, the patent achieves better control over the coupling area with the control gate, allowing optimization of the gate coupling ratio without requiring a complete redesign of the fabrication process.
2Object-affected harmful factors
If floating gate-floating gate capacitance is decreased, then interference is suppressed, but gate coupling ratio is reduced
Solution Approach 1:
The patent applies different properties to different regions of the floating gate structure. The floating gate has enhanced overlap and coupling in regions where it interacts with the control gate, while maintaining appropriate spacing and reduced capacitance in regions where floating gates are adjacent to each other. This local differentiation allows suppressing interference between floating gates while preserving high gate coupling ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the gate coupling ratio, reducing the required operating voltage and suppressing interference between floating gates without the need for additional lithography processes, allowing for more compact and efficient flash memory device fabrication.
Implementation Method 1
A chemical-mechanical polishing process is performed to planarize the first conductive layer
Implementation Method 2
the step of forming a first conductive layer overlaying the substrate comprises performing a physical vapor deposition (PVD) process
Implementation Method 3
the step of forming a first conductive layer overlaying the substrate comprises performing a chemical vapor deposition process (CVD)
Implementation Method 4
the step of removing the portion of the isolation structures comprises performing a wet etching process
Implementation Method 5
the step of removing the portion of the isolation structures comprises performing a dry etching process
Data Source
AI summary
The present invention provides a method for improving gate coupling ratio of a flash memory device and a protruding floating gate is formed. First, a substrate having a plurality of isolation structures is formed. Then, a first conductive layer is formed overlaying the substrate. A chemical-mechanical polishing process is performed to planarize the first conductive layer. After that, a portion of the isolation structures is removed, and a second conductive layer is formed overlaying the first conductive layer and the isolation structures. Finally, a lithography process with a photomask can be used to define a mask that covers the first conductive layer and the second conductive layer, and then an insulating layer is deposited overlaying the substrate, so that a third conductive layer is formed overlaying the insulating layer.