Protruding Interconnect Contacts for Low-Resistance IC Layer Coupling
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Solution Overview
Problem
Integrated circuits face challenges in miniaturizing interconnect features, leading to increased interlayer resistance and overlay errors due to smaller landing areas and contact areas, which affect the reliability of electrical connections.
Innovation Solution
The formation of conductive interconnect features that extend through and above dielectric interconnect material, providing a larger contact area by coupling to both top and side surfaces, and pulling back the liner from the side surface of lower-level conductive features to reduce resistance, allowing for reliable electrical connections despite overlay errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect features are miniaturized to increase functional density, then production efficiency is improved and costs are lowered, but interlayer resistance increases and manufacturing precision deteriorates due to smaller landing areas and contact areas
Solution Approach 1:
The patent extends conductive interconnect features vertically above the dielectric layer surface, transitioning from a planar two-dimensional contact to a three-dimensional protruding structure. This dimensional change increases the contact area between interconnect layers without increasing the lateral footprint, thereby maintaining electrical connection reliability while enabling further miniaturization and increasing functional density.
Solution Approach 2:
The patent forms a liner structure around the conductive interconnect features before the final etching process. This preliminary liner formation protects the conductive material during subsequent processing steps, preventing damage to the protruding features and ensuring their structural integrity, which maintains manufacturing precision while enabling the protruding geometry that reduces interlayer resistance.
2Length of stationary object
If interconnect features are miniaturized, then geometry size is decreased and functional density is increased, but manufacturing precision deteriorates due to smaller landing areas
Solution Approach 1:
By extending conductive features vertically above the dielectric layer, the patent creates a protruding structure that provides a larger target area for subsequent layer alignment. This vertical extension compensates for the reduced lateral dimensions, maintaining manufacturing precision even as geometry size decreases and functional density increases.
Solution Approach 2:
The patent modifies the geometric parameters of interconnect features by creating protrusions that extend above the dielectric layer surface. This parameter change increases the effective contact area and landing area without increasing the lateral footprint, thereby maintaining manufacturing precision while enabling further miniaturization of the overall device geometry.
3Productivity
If conductive features are made smaller to increase density, then functional density is improved, but interlayer resistance increases
Solution Approach 1:
The patent creates protruding conductive features that extend vertically above the dielectric layer, transforming the contact interface from a planar surface to a three-dimensional structure. This dimensional change increases the contact area between interconnect layers without increasing the lateral footprint, thereby reducing interlayer resistance while maintaining high functional density through continued miniaturization.
Solution Approach 2:
The patent forms a liner structure that surrounds the conductive interconnect features, creating a nested configuration where the liner is embedded within or around the conductive material. This nested structure protects the conductive features during processing and may provide additional conductive pathways, reducing interlayer resistance while maintaining the miniaturized geometry required for high functional density.
Data Source
AI summary
Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.