Protruding Traces and Bumps Prevent Voids in Semiconductor Packages
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Solution Overview
Problem
The existing quad flat non-leaded semiconductor packages face issues with insufficient bonding strength between bumps and traces due to co-planarity, leading to voids and low yield during encapsulation.
Innovation Solution
A semiconductor package design where traces and connection pads are protruded from the insulating layer, allowing bumps to encapsulate them, and an encapsulant is formed to increase spacing for easier flow and prevent voids, improving bonding strength and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the traces and connection pads are co-planar with the insulating layer, then the manufacturing process is simplified, but the bonding strength between bumps and traces is insufficient
Solution Approach 1:
The patent transitions from a two-dimensional co-planar arrangement to a three-dimensional protruding structure. The traces and connection pads extend vertically from the insulating layer surface, creating height differences that enable the bumps to wrap around and encapsulate them. This dimensional change allows the bonding interface to engage multiple surfaces of the traces rather than just a single planar contact point, significantly improving bonding strength while maintaining manufacturing feasibility through standard PCB fabrication processes.
2Device complexity
If the traces are co-planar with the insulating layer, then the structure is simpler, but the encapsulant cannot flow easily between traces, causing voids and low yield
Solution Approach 1:
By elevating the traces and connection pads above the insulating layer surface, the patent creates vertical spacing and channels that facilitate encapsulant flow. The protruding structures act as flow guides, directing the encapsulant material between adjacent traces and ensuring complete filling without trapping air voids. This three-dimensional configuration maintains reasonable structural complexity while dramatically improving productivity through enhanced material flow characteristics.
3Ease of manufacture
If the bumps only contact the top surface of co-planar traces, then the manufacturing process is easier, but the bonding area is insufficient leading to weak bonds
Solution Approach 1:
The patent implements a nested configuration where the bumps envelop the protruding traces and connection pads. Instead of simple surface contact, the bumps wrap around the vertical sides and top surfaces of the traces, creating a multi-faceted bonding interface. This nesting arrangement increases the effective bonding area significantly, allowing the bumps to mechanically interlock with the traces from multiple directions, thereby strengthening the bond while remaining compatible with existing bumping and assembly processes.
Data Source
AI summary
This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.