Protruding Word Line Layout for DRAM Overlay Error Tolerance
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) manufacturers face challenges in shrinking memory cell area due to word line spacing errors, leading to electrical leakage between the word line and channel layer during the lithography process.
Innovation Solution
A semiconductor device design featuring a word line with a protruding portion, allowing for greater overlay error tolerance during patterning, which prevents electrical leakage by forming an opening for the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory cell area is shrunk to improve integration density, then productivity and miniaturization are improved, but the spacing between word line and channel layer is reduced, causing electrical leakage due to overlay errors
Solution Approach 1:
The word line structure is made asymmetric by adding a protruding portion that extends toward the channel layer. This asymmetric design creates an enlarged opening area that compensates for lithography overlay errors, allowing the memory cell to be shrunk while maintaining adequate electrical isolation between the word line and channel layer.
Solution Approach 2:
The solution addresses the two-dimensional spacing problem by introducing a dimensional extension through the protruding portion of the word line. This extension in the lateral direction creates additional space for the opening, effectively solving the spacing issue without further reducing the vertical channel dimensions.
2Reliability
If the spacing between word line and channel layer is increased to prevent electrical leakage, then reliability is improved, but the memory cell area increases, reducing productivity
Solution Approach 1:
Instead of uniformly increasing spacing around the channel layer, the asymmetric protruding portion of the word line provides targeted spacing extension only where needed for electrical isolation. This allows adequate spacing for reliability while minimizing the overall memory cell area footprint.
Solution Approach 2:
The protruding portion provides localized spacing enhancement at the critical interface between word line and channel layer, rather than uniformly increasing spacing throughout the entire cell structure. This local quality approach prevents electrical leakage while maintaining compact overall dimensions.
3Manufacturing precision
If the protruding portion is added to the word line to allow greater overlay error, then manufacturing precision requirements are relaxed, but device complexity increases
Solution Approach 1:
The asymmetric protruding portion is integrated into the word line structure during the metallization formation process. While the shape is asymmetric, it follows a simple geometric extension that can be implemented with standard lithography and deposition techniques, adding minimal complexity to the manufacturing process.
Solution Approach 2:
The protruding portion is formed as part of the word line metallization layer before subsequent patterning and deposition steps. This preliminary formation of the extended word line structure simplifies later processing steps and reduces the overall manufacturing complexity compared to adding the protrusion as a separate post-processing feature.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a conductive layer on the substrate; patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer has a first protruding portion protruding toward the second metallization layer; and forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.