Semiconductor Memory Protrusion Pads for Contact Region Reliability
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Solution Overview
Problem
The integration of 2D semiconductor memory devices is limited due to the high cost of minute pattern forming technologies, which restricts their performance and price efficiency, while 3D devices aim to overcome this by stacking memory cells in a vertical direction but face challenges in contact region reliability.
Innovation Solution
The semiconductor memory device incorporates a substrate with a cell array region and a contact region featuring a stacking structure with insulating layers and gate electrodes, including a stepwise structure in the contact region, where gate electrodes have base and protrusion pads to enhance reliability and prevent short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2D semiconductor memory devices use minute pattern forming technologies to increase integration, then integration is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from 2D planar memory devices to 3D vertical memory devices by stacking multiple memory cell layers vertically. This dimensional change allows integration to be determined by the number of stacked layers rather than by minimizing the area of individual memory cells, thereby avoiding the need for expensive minute pattern forming technologies while achieving high integration.
2Productivity
If 3D semiconductor memory devices stack memory cells vertically to improve integration, then integration is improved, but contact region reliability deteriorates
Solution Approach 1:
The contact region is segmented into multiple distinct components: a lower contact plug extending from the substrate to the first insulating layer, and an upper contact plug extending from the second insulating layer to the protrusion pad. This segmentation allows each contact plug to be independently formed and optimized, ensuring reliable electrical connection at each interface while accommodating the vertical stacking structure.
Solution Approach 2:
The lower contact plug is formed in advance before the memory cell layers are stacked, establishing a pre-positioned electrical connection path from the substrate. This preliminary action ensures that the contact region is properly prepared and positioned before the complex vertical stacking process, thereby maintaining connection reliability throughout the 3D structure assembly.
3Stability of the object's composition
If gate electrodes are extended to contact region with stepwise structure, then connection stability is improved, but device complexity increases
Solution Approach 1:
The gate electrode structure exhibits local quality variations: in the cell array region, the gate electrode has a standard configuration, while in the contact region, it develops a stepwise structure with exposed portions at different levels. This localized structural differentiation allows the gate electrode to maintain stable electrical connection in the contact region while preserving the standard memory cell operation in the cell array region, without requiring complex modifications throughout the entire device.
Data Source
AI summary
Disclosed is a semiconductor memory device may include a substrate including a cell array region and a contact region and a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate. The stacking structure may include a stepwise structure in the contact region. Ones of the plurality of gate electrodes may include a respective pad unit that comprises a step of the stepwise structure. At least one of the pad units may include a base pad and a protrusion pad on the base pad. The protrusion pad may be between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode.