Proximal Pixel Processing Architecture for High-Frame-Rate Imaging
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Solution Overview
Problem
Conventional digital image capture and processing systems face challenges in achieving high frame rates due to the need for high-speed data transfer and processing of large volumes of pixel data, leading to increased complexity, cost, power consumption, and size, especially with large image sensor arrays and complex algorithms.
Innovation Solution
A distributed, parallel image capture and processing architecture where a large array of computational circuits is placed proximal to the pixel array, performing computations in parallel on pixel values, thereby reducing the need for massive data transfer to a CPU and alleviating timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pixel data is transferred to a CPU for processing, then image processing can be performed with high flexibility, but data transfer speed requirements and system complexity increase dramatically
Solution Approach 1:
The patent segments the image processing system into two distinct parts: a simple, fixed-function proximal processing unit located near the pixel array that handles basic pixel-level operations, and a remote CPU that handles complex, flexible processing tasks. This segmentation allows the system to maintain flexibility for complex operations while offloading routine processing to reduce data transfer requirements and system complexity.
Solution Approach 2:
The patent introduces an intermediary proximal processing unit that sits between the pixel array and the remote CPU. This intermediary performs preliminary processing of pixel data locally, reducing the volume of data that needs to be transferred to the CPU and simplifying the overall system architecture while maintaining processing flexibility.
2Adaptability or versatility
If pixel data is transferred to a CPU for processing, then comprehensive image processing can be achieved, but power consumption increases
Solution Approach 1:
By segmenting processing tasks between a low-power proximal unit and a high-power remote CPU, the system consumes less overall power. The proximal unit handles energy-efficient, simple operations locally, reducing the need to activate the power-intensive CPU for every processing task.
Solution Approach 2:
The proximal processing unit performs preliminary processing of pixel data before it reaches the CPU. This preliminary action reduces the amount of data and computational load that reaches the power-consuming CPU, thereby reducing overall power consumption while maintaining comprehensive processing capability.
3Productivity
If high-speed data transfer is implemented to meet frame rate requirements, then high frame rates can be achieved, but cost and system complexity increase
Solution Approach 1:
The patent extracts the high-speed data transfer requirement by moving simple processing operations to the proximal unit. This eliminates the need for extremely high-speed data transfer between the pixel array and CPU, as much of the processing is now performed locally where data is already available.
Solution Approach 2:
By performing preliminary processing at the proximal unit, the system reduces the volume and complexity of data that needs to be transferred at high speeds to the CPU, thereby achieving high frame rates without requiring excessively complex and costly high-speed transfer infrastructure.
4Device complexity
If computational circuits are placed proximal to pixels, then data transfer requirements are reduced, but circuit space and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by placing simplified computational circuits with specific, dedicated functions proximal to the pixel array rather than using a uniform, complex processing architecture throughout the system. This localized approach reduces overall manufacturing complexity while achieving the benefit of reduced data transfer requirements.
Data Source
AI summary
A distributed, parallel, image capture and processing architecture provides significant advantages over prior art systems. A very large array of computational circuits—in some embodiments, matching the size of the pixel array—is distributed around, within, or beneath the pixel array of an image sensor. Each computational circuit is dedicated to, and in some embodiments is physically proximal to, one, two, or more associated pixels. Each computational circuit is operative to perform computations on one, two, or more pixel values generated by its associated pixels. The computational circuits all perform the same operation(s), in parallel. In this manner, a very large number of pixel-level operations are performed in parallel, physically and electrically near the pixels. This obviates the need to transfer very large amounts of pixel data from a pixel array to a CPU/memory, for at least many pixel-level image processing operations, thus alleviating the significant high-speed performance constraints placed on modern image sensors.