Proximity-Aware Circuit Design for Semiconductor Yield Optimization
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Solution Overview
Problem
Current methods for handling well proximity effects in semiconductor circuit design either ignore these effects, leading to potential circuit failure, or use conservative guardbanding which results in area penalties, or involve iterative processes causing design time penalties, and do not effectively address other layout-style effects like STI stress and channel stress.
Innovation Solution
A computer-implemented method for proximity-aware circuit design that determines set of layout constraint values using a layout effect model to optimize device placement and routing, incorporating models for well proximity and STI stress to satisfy performance and yield goals, allowing for proactive design that minimizes area and design time penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conservative guardbanding is used to handle well proximity effects, then circuit reliability is improved, but area increases
Solution Approach 1:
The patent applies preliminary action by calculating and determining layout constraints before the actual layout design process. The system computes well proximity effects and determines minimum spacing requirements in advance, allowing the layout to be created without needing conservative guardbands, thus maintaining reliability while minimizing area.
Solution Approach 2:
The patent changes the parameter approach from using fixed conservative guardband distances to dynamically calculated layout constraints based on actual device positions and well proximity effects. The system adjusts spacing parameters individually for each device based on its specific location and the calculated proximity effects, optimizing the balance between reliability and area.
2Reliability
If iterative design processes are used to handle proximity effects, then circuit reliability is improved, but design time increases
Solution Approach 1:
The patent eliminates iterative processes by performing preliminary calculations of well proximity effects and determining layout constraints before the layout design begins. The system calculates the effects in advance and uses these pre-determined constraints to guide the layout creation, ensuring reliability without requiring time-consuming iterations.
Solution Approach 2:
The patent incorporates feedback mechanisms where the calculated well proximity effects and layout constraints are fed back into the layout design process as guiding principles. This feedback approach allows the design to be created in a single pass using accurate pre-calculated data, avoiding the need for iterative adjustments while maintaining reliability.
3Device complexity
If well proximity effects are ignored in circuit design, then design simplicity is maintained, but circuit functionality may be compromised
Solution Approach 1:
The patent introduces new design parameters that quantify well proximity effects for each device. By calculating these parameters and using them to determine layout constraints, the system maintains design simplicity while accounting for proximity effects. The added complexity is minimal compared to the risk of functional failure from ignoring these effects.
Data Source
AI summary
A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.