Proximity Data Processing Module Multi-Channel Bandwidth Optimization

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Solution Overview

Problem

Current storage devices face limitations in data processing performance due to restricted bandwidth between the host and the storage device, which hampers efficient data processing.

Innovation Solution

The implementation of a storage device with a core processor adjacent to multiple memory cells, utilizing multiple channels for data access and processing, and an internal splitter to merge data from multiple channels, enhancing data processing efficiency by converting physical addresses to logical addresses for simultaneous data loading and reading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single channel is used for data access between host and storage device, then device complexity is reduced, but memory bandwidth efficiency deteriorates

Engineering Contradiction:
Improvechannel configuration complexityVSAvoidmemory bandwidth efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The data access channel is segmented into multiple parallel channels (first channel and second channel) to increase memory bandwidth efficiency. Each channel can independently transfer data, allowing simultaneous data loading and reading operations that improve overall productivity without requiring complex coordination

Inventive Principle:
Principle #1Segmentation

2Device complexity

If physical addresses are allocated sequentially per channel, then address management is simple, but data processing performance deteriorates

Engineering Contradiction:
Improveaddress management complexityVSAvoiddata processing performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The address allocation approach transitions from a sequential one-dimensional pattern to a two-dimensional matrix pattern. Physical addresses are allocated in rows across channels, and logical addresses are formed by combining channel identifiers with row indices, enabling efficient mapping that improves data processing performance while maintaining manageable complexity through systematic address translation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of energy

If data is loaded and read sequentially through single channel, then channel resource usage is low, but bandwidth efficiency deteriorates

Engineering Contradiction:
Improvechannel resource utilization efficiencyVSAvoiddata processing throughput
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The system enables continuous data processing by simultaneously loading data through the first channel and reading data through the second channel. This parallel operation eliminates idle periods in the data processing pipeline, maintaining continuous useful action across multiple channels to improve both throughput and resource utilization efficiency

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20240126444A1Storage device, computing system and proximity data processing module with improved efficiency of memory bandwidth
Publication Date: 2024.04.18 SK HYNIX INC
  • US20240126444A1 patent drawing
  • US20240126444A1 patent drawing
  • US20240126444A1 patent drawing

AI summary

A method is provided in which a core processor located adjacent to a memory and processing data of the memory in a proximity data processing scheme reads and processes the data of the memory by simultaneously using a plurality of channels used by the memory. Since data processing is performed simultaneously using a total bandwidth between the memory and the core processor, the efficiency of the proximity data processing scheme by the core processor may be improved.