Proximity Optical Memory Module Bandwidth Bottleneck
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Solution Overview
Problem
Current memory modules face limitations in bandwidth due to the disparity between processing power and memory access, particularly in multi-core processors, where the number of electrical interconnects and wiring channels restrict the scalability and efficiency of memory access, leading to bottlenecks in high-performance computer systems.
Innovation Solution
The integration of a proximity communication system with optical interfaces between memory chips and an interface chip, allowing for high-speed data transfer through capacitive or optical links, thereby increasing bandwidth and reducing power consumption, while also providing a more reliable and economical packaging method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrical interconnects and wiring channels are used in conventional memory modules, then the structure is simple and easy to manufacture, but the bandwidth is limited and cannot keep pace with processing power improvements
Solution Approach 1:
The patent replaces electrical interconnects with optical interconnects. Specifically, optical channels with transmitters and receivers are used instead of electrical wiring channels to connect memory modules to the memory controller. This substitution enables much higher bandwidth (potentially terabits per second) while overcoming the limitations of electrical signal propagation and pin count, directly resolving the contradiction between bandwidth and interface complexity.
2Productivity
If the number of parallel electrical interconnects is increased to improve bandwidth, then memory access speed improves, but the pitch of connectors and wiring density become limiting factors
Solution Approach 1:
The patent substitutes optical channels for electrical interconnects, eliminating the physical constraints of connector pitch and wiring density. Optical fibers or waveguides can be bundled or routed with much smaller effective pitch than electrical connectors, allowing significantly higher channel counts in the same physical space, thus improving memory access speed without hitting connector pitch limitations.
Solution Approach 2:
The patent moves the interconnection medium from the planar dimension (PCB trace routing) to the vertical/three-dimensional dimension (optical fibers running through or alongside the module). This dimensional transition allows for much higher density interconnects that are not constrained by traditional PCB routing rules and connector pitch requirements.
3Productivity
If optical interfaces are used between memory controller and memory modules, then power consumption and bandwidth are improved, but the I/O bandwidth of memory chips becomes the limiting factor
Solution Approach 1:
The patent segments the memory module into multiple independent memory chips, each with its own optical interface. Instead of one high-bandwidth interface, multiple lower-bandwidth interfaces are used in parallel. This segmentation allows the total bandwidth to scale with the number of chips while keeping each individual chip's I/O requirements manageable and matching them to the optical channel capabilities.
Solution Approach 2:
The patent makes each memory chip universally interfaceable with optical channels through standardized optical interfaces. Each chip can independently communicate over optical channels, and the system can dynamically allocate and aggregate bandwidth from multiple chips to meet varying memory demands, making the overall system adaptable and scalable without being constrained by a single chip's I/O bandwidth.
4Device complexity
If a single I/O port is used on DRAM chips for multiple memory banks, then the chip structure is simplified, but bandwidth is limited as only one bank can be accessed at a time
Solution Approach 1:
The patent divides the memory system into multiple independent memory banks across multiple chips, each with its own optical interface. This segmentation allows simultaneous access to multiple banks through parallel optical channels, eliminating the sequential access bottleneck of single-I/O designs while keeping individual chip structures relatively simple.
Solution Approach 2:
The patent enables continuous memory access by allowing multiple memory banks to be accessed simultaneously through parallel optical interfaces. While one bank is being read, another can be written to, and a third can be accessed, creating continuous useful action without the idle wait states inherent in single-I/O sequential access designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances memory module bandwidth, power efficiency, and capacity by enabling simultaneous access to multiple memory banks without the need for multiplexing, achieving peak memory bandwidths that match the external optical channel capabilities and providing redundancy and fault tolerance.
Implementation Method 1
proximity communication including capacitive coupling between transmitting and receiving elements formed on the chips
Implementation Method 2
an optical interface between the memory chips and an interface chip, allowing for high-speed data transfer through capacitive or optical links
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.