Proxy Logic for PCI Bus Cycle Interception
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Solution Overview
Problem
Undesirable bus behavior on computer buses, such as PCI buses, occurs due to target devices being unable to respond correctly to cycles, leading to bus lock-ups and contention, especially when management processors are unaware of the main CPU's disabling of devices or when devices are in initialization or test modes.
Innovation Solution
The implementation of proxy logic that monitors bus activity and blocks or aborts cycles intended for non-responsive target devices, using techniques like blocking the FRAME# signal or providing placebo data to prevent incorrect responses and resolve contention before the subtractive decode agent intervenes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the target device is allowed to respond to all bus cycles, then the device can perform its intended function, but the bus may lock up or exhibit undesirable behavior when the device is in initialization or test modes
Solution Approach 1:
The patent introduces a bridge logic device that acts as an intermediary between the bus and the target device. This bridge logic monitors bus cycles and intercepts those intended for the target device, preventing the target device from responding when it is in initialization or test modes. The bridge logic serves as a protective mediator that filters harmful bus interactions before they reach the vulnerable target device, thereby preventing bus lock-ups while allowing normal operation during functional modes.
Solution Approach 2:
The patent implements preliminary detection and blocking of bus cycles by the bridge logic before the target device can respond. The bridge logic proactively identifies cycles intended for the target device and blocks them in advance when the target device is in vulnerable states (initialization or test modes). This preliminary action prevents the harmful response from occurring in the first place, rather than reacting after the problem arises.
2Adaptability or versatility
If the management processor is given autonomous access to PCI bus devices, then it can access devices even when the main CPU is non-operational, but the management processor may be unaware that devices have been disabled by the main CPU
Solution Approach 1:
The bridge logic device serves as an intermediary that monitors and controls access to the target device from both the main CPU and the management processor. It maintains awareness of the target device's operational state and filters cycles from either processor accordingly. This intermediary mechanism ensures that autonomous access by the management processor does not lead to unreliable responses when the target device is disabled or in non-functional modes.
3Reliability
If the subtractive decode agent is used to claim cycles when no other device responds, then bus operation is ensured, but non-responsive target devices may still cause contention before the subtractive decode agent intervenes
Solution Approach 1:
The bridge logic performs preliminary interception and blocking of bus cycles intended for the target device before the cycles can proceed to the subtractive decode agent. By detecting and blocking these cycles in advance at the bridge level, the system prevents the time-consuming contention sequence from occurring, thereby reducing bus contention duration while maintaining continuous bus operation through the bridge logic's alternative handling of blocked cycles.
Data Source
AI summary
A system includes proxy logic which detects situations which, unless action is taken, would result in undesirable bus behavior. In one embodiment, the target device of a bus cycle includes proxy logic which determines when the target device is unable to respond correctly to a bus cycle. In this situation, the proxy logic blocks a bus signal from being received by the addressed logic in the target device, thereby preventing the target device from responding at all. In another embodiment, proxy logic is located external to the target device and determines when the target device has not responded to a cycle intended for it. When this condition has occurred, the proxy logic responds to the cycle before the bus's subtractive decode agent has a chance to claim the cycle. The proxy logic's response may be to return bogus data or terminate or abort the cycle.