Proxy Memory Circuit Offloads Decryption From Processor
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Solution Overview
Problem
Existing systems that require plaintext information to remain on a single chip for security face inefficiencies due to specialized CPUs performing decryption tasks, which slows down core application processes and often lack sufficient on-chip memory for storing application information.
Innovation Solution
A circuit arrangement with an interconnect circuit, processor, proxy memory circuit, and decryption circuit that translates and decrypts off-chip encrypted data, offloading decryption processing from the processor and allowing customizable cryptographic algorithms and memory layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If specialized CPUs are employed to authenticate and decrypt information from off-chip memory, then security is improved, but processing speed deteriorates
Solution Approach 1:
The patent segments the processing functions by separating the decryption circuit from the main processor. The decryption circuit is a dedicated hardware component that handles decryption tasks independently, while the processor focuses on executing application instructions. This segmentation allows parallel processing of decryption and computation, improving overall system speed without compromising security.
Solution Approach 2:
The patent introduces a proxy memory circuit as an intermediary between the processor and the encrypted off-chip memory. This proxy memory circuit manages the decryption operations and data transfer, acting as a mediator that offloads the decryption burden from the processor. The intermediary handles the cryptographic operations while the processor continues its core tasks, resolving the speed-security tradeoff.
2Reliability
If plaintext information is stored on a single chip, then security is improved, but memory capacity deteriorates
Solution Approach 1:
The patent extracts the memory storage function from the chip by utilizing off-chip encrypted memory. Instead of storing plaintext information on-chip, the system stores encrypted data in external memory devices. This extraction allows the chip to maintain security while accessing large容量的 off-chip memory, effectively resolving the contradiction between security and memory capacity.
Solution Approach 2:
The patent implements a proxy memory circuit that creates a virtual copy of the off-chip encrypted memory space within the chip. This proxy memory provides an interface that makes the off-chip encrypted storage appear as if it were local memory to the processor, enabling the system to access large memory capacities while maintaining the security benefits of encrypted off-chip storage.
3Device complexity
If the same processor executes instructions and performs decryption, then device complexity is reduced, but productivity deteriorates
Solution Approach 1:
The patent segments the processing architecture into distinct functional units: a main processor for executing application instructions and a dedicated decryption circuit for cryptographic operations. This segmentation increases device complexity slightly but dramatically improves productivity by enabling parallel execution of computation and decryption tasks, eliminating the bottleneck of sequential processing.
Solution Approach 2:
The decryption circuit is designed as a universal cryptographic processing unit that can handle various encryption algorithms and data types. This multi-functional decryption circuit serves both security purposes and data processing needs, improving overall system productivity without requiring multiple specialized processors. The universal decryption unit handles diverse cryptographic operations efficiently.
Data Source
AI summary
A disclosed circuit arrangement includes an interconnect circuit, a processor, a first memory circuit, a proxy memory circuit, and a decryption circuit. The interconnect circuit receives a first transaction from one of the one or more processors and transmits the first transaction to the proxy memory circuit in response to a first address in a first transaction. The proxy memory circuit translates the first address into a second address of the first memory circuit, generates a second transaction including the second address, transmits the second transaction to the interconnect circuit, and receives encrypted data from the first memory circuit in a response to the second transaction. The decryption circuit decrypts the encrypted data into decrypted data, and the proxy memory circuit transmits the decrypted data to the one processor in a response to the first transaction.