PRPG Seed Generation via Delayed Justification
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Solution Overview
Problem
Current methods for testing integrated circuits (ICs) face inefficiencies due to high test pattern volume and time requirements, especially with increasing complexity, leading to insufficient scan-alone scan testing for controlling test costs and maintaining high defect coverage.
Innovation Solution
A method for generating pseudo-random pattern generator (PRPG) seeds through delayed justification and preprocessing techniques, including gate modification restrictions, dynamic value considerations, and fanout allowance, to enhance scan compression without affecting test coverage or requiring hardware support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic ATPG is used to generate test patterns, then fault coverage close to 100% is achieved, but test pattern volume and application time increase significantly
Solution Approach 1:
The patent segments the test pattern generation process into two phases: (1) generating a reduced set of test patterns using deterministic ATPG with xheadlines and preprocessing, and (2) applying PRPG-based compression to these patterns. This segmentation allows the system to benefit from both deterministic fault coverage and compressed test data volume, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent changes the parameter representation from full test patterns to compressed PRPG seed patterns. By transforming test patterns into a compressed format using PRPG (pseudorandom pattern generator) with seeds derived from xheadlines and preprocessing, the system maintains fault coverage while significantly reducing test pattern volume and application time.
2Reliability
If scan chains are loaded with predetermined logic signals, then test patterns can be applied to detect faults, but loading process requires significant time (at least 500 clock cycles for longest scan chain)
Solution Approach 1:
The patent performs preliminary compression of test patterns into PRPG seed format before application to scan chains. By pre-compressing the test patterns using PRPG with seeds derived from xheadlines and preprocessing, the system reduces the amount of data that needs to be loaded into scan chains, thereby reducing loading time while maintaining fault detection capability.
Solution Approach 2:
The patent uses PRPG (pseudorandom pattern generator) to generate compressed test patterns from a reduced set of seed patterns. This copying approach allows the same fault detection capability to be achieved with fewer test patterns, reducing the loading time required for scan chains while maintaining reliability.
3Reliability
If exhaustive test is performed with 2N input patterns, then all potential faults are detected, but test cost becomes commercially impractical as number of inputs increases
Solution Approach 1:
The patent segments the exhaustive test approach into two parts: (1) using deterministic ATPG to generate a reduced set of test patterns that achieve close to 100% fault coverage, and (2) applying PRPG-based compression to this reduced set. This segmentation maintains fault detection completeness while dramatically reducing test cost by avoiding the need to apply all 2N exhaustive patterns.
Solution Approach 2:
The patent changes the test pattern representation from full exhaustive patterns to compressed PRPG seed patterns. By transforming the test data into a compressed format using PRPG with seeds derived from xheadlines and preprocessing, the system maintains fault detection completeness while significantly reducing test cost and data volume.
Data Source
AI summary
An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.