PRPG Scan Test System Clock Cycle Freezing
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Solution Overview
Problem
As the complexity and size of integrated circuits increase, the volume of test data and the time required for scan testing also grow, leading to higher testing costs and longer time-to-market.
Innovation Solution
A Pseudo-Random Pattern Generator (PRPG) based scan test system that modifies the bit distribution of test patterns by freezing specific clock cycles, allowing for more efficient test pattern generation and application, thereby reducing test time and improving fault detection probability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If test data compression techniques are used to reduce test data volume, then test data volume is reduced, but test application time increases
Solution Approach 1:
The system dynamically adjusts the distribution of care-bits and don't-care-bits in test patterns by selectively freezing clock cycles of the PRPG. This dynamic modification optimizes the balance between test data compression effectiveness and test application speed, allowing the system to adapt to different testing scenarios and circuit requirements.
Solution Approach 2:
The invention changes the temporal parameters of test pattern generation by freezing specific clock cycles of the PRPG. This parameter modification alters the bit distribution in generated test patterns, enabling optimization of both compression ratio and test application time by controlling when the PRPG updates its state.
2Adaptability or versatility
If the size and complexity of integrated circuits grow, then circuit functionality improves, but test time increases
Solution Approach 1:
The test system segments the test pattern generation process by separating the PRPG operation into active clock cycles and frozen clock cycles. This segmentation allows different portions of the test pattern to be generated with different bit distributions, enabling efficient testing of complex circuits by optimizing each segment's contribution to overall test effectiveness.
Solution Approach 2:
The system employs periodic freezing of PRPG clock cycles at strategically selected intervals during test pattern generation. This periodic action creates an optimized bit distribution pattern that improves fault detection efficiency in complex circuits while reducing the total test time required compared to continuous PRPG operation.
3Reliability
If conventional scan testing is used to detect faults, then fault detection is achieved, but testing costs and time-to-market increase
Solution Approach 1:
The system performs preliminary optimization of test pattern bit distribution before actual test application by controlling the PRPG clock cycles in advance. This preliminary action ensures that the generated test patterns have optimal care-bit distribution for the specific circuit being tested, improving fault detection probability while reducing the time required for subsequent test execution.
Data Source
AI summary
In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.