Stacked Pseudo CFET Resistor Layout for Parasitic Capacitance Control
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Solution Overview
Problem
There is a lack of detailed investigation into specific configurations for using complementary field effect transistors (CFETs) as resistor elements in semiconductor devices, limiting their finer microfabrication capabilities and resistance properties.
Innovation Solution
A semiconductor device configuration is developed, incorporating pseudo CFETs with pseudo N-channel and P-channel MOS transistors, where the pseudo P-channel MOS transistor is formed over the pseudo N-channel MOS transistor, and connected in series to function as resistors, with specific power line and semiconductor region configurations to enhance microfabrication and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CFETs are used as resistor elements, then finer microfabrication is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance effect by configuring the CFET gate electrode to extend beyond the source and drain regions, effectively isolating the parasitic capacitance from the resistor element's electrical characteristics and preventing its harmful influence on device performance
Solution Approach 2:
The gate electrode serves as an intermediary structure that mediates between the source and drain regions. By extending the gate electrode beyond these regions, it acts as a shielding element that reduces parasitic capacitance coupling between adjacent structures while maintaining the desired resistance properties
2Productivity
If CFETs are stacked over substrate, then device integration is improved, but resistance control becomes difficult
Solution Approach 1:
The patent applies local quality by configuring the gate electrode with different dimensions and positions relative to the source and drain regions. The gate electrode width, length, and extension beyond source/drain regions are specifically optimized to achieve precise resistance control (1kΩ to 10MΩ) while maintaining stacked CFET integration
Solution Approach 2:
The patent utilizes parameter changes by adjusting the gate electrode's physical dimensions (width, length, extension distance) and electrical characteristics to control the resistor element's resistance value. This allows precise resistance tuning across a wide range (1kΩ to 10MΩ) while maintaining the stacked CFET structure for high device integration
Data Source
AI summary
A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.