Pseudo-Channel Memory with Shared I/O for Lower DDR Latency
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Solution Overview
Problem
Existing DDR systems exhibit high latency due to differences in write/read burst lengths and IO schemes, particularly at lower clock frequencies, which is not acceptable for applications requiring low latency.
Innovation Solution
Employing pseudo channel selection devices to concurrently connect multiple pseudo channels to shared IOs via wider internal data buses, allowing concurrent data transfer using multiplexers, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional DDR systems use standard write/read burst lengths and IO schemes, then system compatibility and ease of operation are maintained, but latency increases and performance deteriorates
Solution Approach 1:
The patent segments the memory system into multiple pseudo-channels (first pseudo-channel, second pseudo-channel, etc.), each with dedicated data buses. This segmentation allows independent optimization of each channel's burst length and IO scheme, enabling low-latency operations without complicating the entire system. Each pseudo-channel can operate with optimized parameters while maintaining overall system compatibility.
Solution Approach 2:
The patent implements dynamic operation modes that can switch between different configurations. The memory system can dynamically select between standard mode (for compatibility) and low-latency mode (for performance), adjusting burst lengths and IO schemes based on operational requirements. This dynamic adaptability resolves the contradiction by allowing the system to optimize latency when needed while maintaining ease of operation during normal use.
2Use of energy by moving object
If LPDDR systems use power-saving approaches, then energy consumption decreases, but latency increases and performance is degraded
Solution Approach 1:
The patent employs periodic activation of pseudo-channels, where only the required pseudo-channel is activated at any given time rather than keeping all channels continuously active. This periodic action approach allows the memory system to maintain power-saving characteristics while achieving low latency when a pseudo-channel is actively accessed, as the active channel can use optimized burst lengths and IO schemes without affecting overall power consumption.
3Productivity
If multiple pseudo channels are connected to shared IOs via wider internal data buses, then data transfer width and burst length increase improving performance, but device complexity increases
Solution Approach 1:
The patent merges multiple pseudo-channels to share common IO resources through a pseudo-channel selection device. Instead of providing dedicated IO paths for each pseudo-channel, the invention combines them and uses a selection mechanism to route data. This merging approach increases data transfer efficiency by allowing wider effective data buses while managing complexity through resource sharing rather than duplication.
Solution Approach 2:
The patent introduces a pseudo-channel selection device as an intermediary component between the multiple pseudo-channels and the shared IO resources. This mediator manages the connections dynamically, selecting which pseudo-channel connects to which IO at any given time. The intermediary handles the complexity of managing multiple wide data buses, allowing the rest of the system to benefit from increased data transfer efficiency without directly dealing with the complexity.
Data Source
AI summary
A memory system comprises a first bank group communicatively connected to a first internal bus, wherein the first internal bus is configured to communicatively connect to a first input/output (IO), a second bank group communicatively connected to a second internal bus, and a channel selection device configured to selectively communicatively connect the second internal bus to the first IO in a first operation mode or a second IO in a second operation mode in response to the memory system receiving a mode register write command configured to cause the memory system to operate in the first operation mode or the second operation mode.