Pseudo-channeled DRAM Architecture for Bandwidth Scaling
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Solution Overview
Problem
Current DRAM technologies face challenges in increasing bandwidth while maintaining low power consumption and reliability, with existing solutions like module threading, micro-threading, and sub-channel technologies either increasing costs, reducing performance, or requiring additional pins and complex configurations.
Innovation Solution
The implementation of a pseudo-channeled DRAM architecture that allows for two or more pseudo-channels per memory channel, sharing data strobe pins and command address pins between channels, and providing single device data correction, while maintaining the same pin count and reliability as DDR5 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If module threading, micro-threading, or sub-channel technologies are used to increase bandwidth, then bandwidth is improved, but device complexity and pin requirements increase
Solution Approach 1:
The patent makes existing DRAM pins serve multiple functions by implementing pseudo-channeled access. Command address pins and data strobe pins are shared across multiple pseudo-channels, allowing the same physical pins to handle multiple logical channels. This eliminates the need for additional pins while achieving increased bandwidth through software-defined channel multiplexing.
Solution Approach 2:
The patent implements dynamic channel assignment where pseudo-channels are created and managed through control logic that can dynamically allocate and switch between different pseudo-channels. The system can adaptively manage channel assignments based on workload requirements, enabling flexible bandwidth optimization without fixed hardware channel configurations.
2Productivity
If additional pins are added to increase bandwidth, then bandwidth is improved, but ease of manufacture and cost increase
Solution Approach 1:
The patent makes existing DRAM pins serve multiple functions by implementing pseudo-channeled access. Command address pins and data strobe pins are shared across multiple pseudo-channels, allowing the same physical pins to handle multiple logical channels. This eliminates the need for additional pins while achieving increased bandwidth through software-defined channel multiplexing.
3Productivity
If more channels are added to increase bandwidth, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic channel assignment where pseudo-channels are created and managed through control logic that can dynamically allocate and switch between different pseudo-channels. The system can adaptively manage channel assignments based on workload requirements, enabling flexible bandwidth optimization without fixed hardware channel configurations.
Solution Approach 2:
The patent employs time-division multiplexing where multiple pseudo-channels share the same physical pins through periodic time slots. Different pseudo-channels are activated at different time periods, allowing the system to achieve multi-channel bandwidth equivalent performance while keeping only one physical channel active at any given time, thus avoiding the power consumption of continuously active multiple channels.
4Device complexity
If pseudo-channels share command address pins, then device complexity is reduced, but measurement precision of channel identification may be affected
Solution Approach 1:
The patent incorporates control logic that tracks and manages pin assignments across multiple pseudo-channels. The system monitors which pseudo-channel is currently active and maintains accurate state information, ensuring that shared command address pins and data strobe pins are correctly associated with the active pseudo-channel. This feedback mechanism prevents identification errors despite pin sharing.
Data Source
AI summary
An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.