Pseudo Class-AB MOSFET Output Stage for Linearity and Headroom
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Solution Overview
Problem
High drive current applications face challenges in achieving both linearity and power efficiency in circuit design, with class-A structures being inefficient, class-B structures lacking linearity, and class-AB structures having insufficient headroom.
Innovation Solution
A pseudo class-AB structure is implemented with a parallel connection of capacitors and impedance components between the gates of complementary MOS gates, along with a bias circuit that mirrors bias current to the impedance components, maintaining high transconductance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a class-A structure is used, then linearity is improved, but power efficiency deteriorates
Solution Approach 1:
The circuit dynamically switches between class-A and class-AB operation modes based on signal conditions. The first and second capacitors coupled between complementary MOS gates create a pseudo class-AB structure that maintains high transconductance at low frequencies while improving power efficiency, allowing the circuit to adapt its operating characteristics rather than being fixed in one mode
Solution Approach 2:
The patent changes the operating parameters by introducing capacitive coupling between complementary MOS gates, which modifies the transconductance characteristics. This parameter change enables the circuit to maintain high transconductance at low frequencies while operating in a more power-efficient class-AB mode rather than continuous class-A operation
2Use of energy by moving object
If a class-B structure is used, then power efficiency is improved, but linearity deteriorates
Solution Approach 1:
The circuit transitions from static class-B operation to dynamic pseudo class-AB operation. The capacitive coupling between complementary MOS gates enables the circuit to maintain high transconductance at low frequencies, improving linearity while retaining the power efficiency benefits of class-B operation through selective activation of transistor pairs
Solution Approach 2:
By introducing capacitors between complementary MOS gates, the patent changes the voltage and current parameters in the output stage. This modification allows the circuit to achieve high transconductance at low frequencies without requiring continuous biasing of all transistor pairs, thus improving linearity while maintaining power efficiency
3Use of energy by moving object
If a class-AB structure is used, then both linearity and power efficiency are improved, but headroom deteriorates
Solution Approach 1:
The patent implements a dynamic pseudo class-AB structure that only activates the capacitive coupling and associated transistors when low-frequency signals are present. This dynamic operation allows the circuit to achieve improved linearity and power efficiency at low frequencies while maintaining full headroom at high frequencies where the capacitive coupling has minimal effect
Solution Approach 2:
The capacitive coupling between complementary MOS gates creates periodic action at low frequencies, enabling the circuit to achieve improved linearity and power efficiency during low-frequency operation. At high frequencies, the capacitors act as open circuits, preserving the original circuit behavior and headroom characteristics
Data Source
AI summary
A circuit with a pseudo class-AB structure is shown. The circuit has an output stage, a first capacitor, and a first impedance component. The output stage has a first PMOS (p-type Metal-Oxide-Semiconductor Field-Effect Transistor) and a first NMOS (n-type MOSFET). The first connection node between the drain terminal of the first PMOS and the drain terminal of the first NMOS is coupled to the first output terminal of the circuit. The first capacitor is coupled between the gate terminal of the first PMOS and the gate terminal of the first NMOS. The first impedance component is coupled in parallel with the first capacitor between the gate terminal of the first PMOS and the gate terminal of the first NMOS.