Pseudo-Complementary Logic Network for Low-Power Thin-Film Circuits
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Solution Overview
Problem
In organic and thin-film transistors, the large difference in mobility between n-type and p-type carriers makes it difficult to integrate transistors into complementary circuits, leading to increased power consumption and insufficient noise margin when only N-type or P-type transistors are used.
Innovation Solution
A pseudo-complementary logic network is implemented using a first logic stage with a pull-up and pull-down circuit of the same type of transistor, where the output of a second logic stage is fed back as input to the first pull-up or pull-down circuit, allowing for complementary operation between the circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only N-type or P-type transistors are used in organic transistors or thin-film transistors, then device integration is simplified, but power consumption increases due to large static current consumption
Solution Approach 1:
The logic circuit is divided into multiple logic stages, with each stage containing separate pull-up and pull-down circuits. This segmentation allows independent control of current paths, enabling complementary operation where one circuit is active while the other is inactive, thus reducing static current consumption while maintaining simplified transistor integration
Solution Approach 2:
The patent implements pseudo-complementary logic by inverting the traditional complementary approach: instead of using different transistor types (N-type and P-type), it uses the same transistor type with pull-up and pull-down circuits that operate in opposite states. This inversion allows single-type transistor integration while achieving low power consumption through complementary operation
2Ease of manufacture
If only N-type or P-type transistors are used without complementary circuit, then manufacturing is simplified, but noise margin becomes insufficient
Solution Approach 1:
Each logic stage is segmented into distinct pull-up and pull-down circuits with separate current paths. This segmentation ensures that only one circuit conducts at a time, providing clear logic level definition and adequate noise margins while maintaining manufacturing simplicity through single-type transistor usage
Solution Approach 2:
The output signal of the second logic stage is fed back as input to the first pull-down circuit, creating a feedback mechanism that ensures proper logic level restoration and maintains noise margins. This feedback arrangement helps prevent signal degradation and ensures reliable operation
Data Source
AI summary
A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.