Pseudo Device Voltage Rule Check in EDA Netlists
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Solution Overview
Problem
Current circuit simulators are unable to intuitively perform voltage rule checks between wirings in back-end-of-line (BEOL) layouts or between different voltage domains, failing to mark or check voltage stress effectively, which is particularly problematic in high-voltage circuit designs and flash memory architectures.
Innovation Solution
A computer-implemented method is introduced that involves inserting pseudo devices with safe operating area (SOA) settings into netlists or circuit schematics, allowing for the examination of voltage rules across specific circuit sections without affecting the original circuits, using an electronic design automation (EDA) platform to perform SOA checks and identify potential violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit simulators perform standard circuit simulation based on Kirchhoff voltage laws and current laws, then the simulation can solve the system of equations to obtain voltage and current values, but the simulation cannot check voltage stress between devices or wirings during the iteration process
Solution Approach 1:
The patent introduces pseudo devices as intermediary elements between real circuit devices. These pseudo devices act as mediators that monitor voltage stress without interfering with the original circuit operation. The pseudo devices capture voltage information from critical nodes and compare it against predefined safety thresholds, enabling voltage rule checking while maintaining the integrity of the original circuit simulation.
Solution Approach 2:
The patent applies preliminary action by pre-configuring pseudo devices with safe operating area (SOA) parameters before circuit simulation begins. The voltage thresholds and safety limits are established in advance, allowing the simulation system to automatically detect violations during the iteration process without requiring post-simulation analysis or complex real-time calculations.
2Reliability
If circuit designers manually monitor nodes to verify voltage rules, then voltage violations can be detected, but the process is error-prone and cannot check voltage stress between multiple devices or metal wirings comprehensively
Solution Approach 1:
The patent implements self-service by enabling the circuit simulation system to automatically perform voltage rule checking without requiring manual intervention from designers. The pseudo devices autonomously monitor voltage stress, compare it against predefined thresholds, and generate warnings for violations. This automated approach eliminates human error and comprehensively checks all critical nodes and wirings throughout the circuit.
Solution Approach 2:
The patent incorporates feedback mechanisms where pseudo devices continuously monitor voltage conditions and provide immediate feedback when voltage stress exceeds safe operating limits. The system generates warning messages that are fed back to the designer, enabling real-time detection and correction of potential voltage violations during the design process.
3Reliability
If standard design rule check tools are used, then basic design rules can be verified, but voltage stress between wirings in back-end-of-line layout and between different voltage domains cannot be checked
Solution Approach 1:
The patent achieves universality by designing pseudo devices that can operate across multiple voltage domains and circuit configurations. The same pseudo device framework can monitor voltage stress in low-voltage domains, high-voltage domains, and mixed-signal circuits simultaneously. The system adapts to different voltage thresholds and SOA parameters based on the specific circuit being analyzed, providing comprehensive coverage for various design scenarios.
Data Source
AI summary
A computer-implemented method of performing voltage rule check in an electronic design automation (EDA) platform is provided in the present invention, including steps of inserting pseudo device with safe operating area (SOA) model setting in a netlist generated by the EDA platform or in a schematic of process design kit (PDK), wherein parameters of the pseudo device and the model are set so that the pseudo device would not affect original circuits in the netlist and the schematic, performing SOA check in the netlist or the schematic through the EDA platform, and examining the warning messages triggered by the pseudo device and the model violating the SOA setting in the SOA check to find out layout sections violating the SOA setting.