Pseudo-Dual Port Memory With Independent Clock Signals
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Solution Overview
Problem
Conventional pseudo-dual port memories using a single input clock signal for both read and write operations can lead to inefficient memory access times due to mismatched operation durations and clock signal duty cycles, resulting in wasted time and reduced maximum clock frequency.
Innovation Solution
Implementing a pseudo-dual port memory with separate clock signals for each port, where the rising edge of one clock initiates a read operation and the rising edge of another clock initiates a write operation, using a time delayed multiplexer and write clock suppressor circuit to adjust and synchronize these operations independently of the clock signal duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single input clock signal is used for both read and write operations, then the memory structure is simpler, but the memory access time efficiency deteriorates due to mismatched operation durations and clock duty cycles
Solution Approach 1:
The single clock signal is segmented into two separate clock signals (first clock signal for read operations, second clock signal for write operations). This allows independent timing control for each operation type, eliminating the waste time caused by duty cycle mismatches while maintaining manageable system complexity through dedicated clocking for each port.
2Reliability
If the falling edge of a single clock signal is used to initiate the second memory operation, then the timing is synchronized, but the maximum clock frequency is reduced due to jitter and time margin requirements
Solution Approach 1:
The first memory operation is initiated in advance by the rising edge of the first clock signal, before the second operation needs to start. This preliminary initiation allows the operation to proceed independently without waiting for clock synchronization, eliminating the need for time margins and enabling higher clock frequencies while maintaining reliable timing through the preliminary start.
3Device complexity
If a single clock signal with fixed duty cycle is used, then the clock generation is simpler, but the operation durations cannot be flexibly adjusted to match actual read and write times
Solution Approach 1:
The clock system transitions from a static single clock signal with fixed duty cycle to dynamic separate clock signals where the first and second clock signals can have independently adjustable duty cycles. This dynamic adaptation allows each clock to be optimized for its specific operation type (read or write), matching the actual operation durations while maintaining relatively simple clock generation through independent oscillators.
Data Source
AI summary
A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.