Pseudo Dual Port Memory Clock Synchronization
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Solution Overview
Problem
Pseudo dual port memories face challenges in efficiently managing read and write operations within a single clock cycle, as they sequentially perform these operations to emulate dual port memory functionality, leading to potential timing issues and inefficiencies.
Innovation Solution
A memory system with a control circuit that generates separate read and write clocks, where the write clock is triggered by the resetting of the read clock in one mode and by the beginning of the memory cycle in another mode, allowing for optimized timing of write operations relative to read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pseudo dual port memory sequentially performs read and write operations to emulate dual port functionality, then memory area is reduced, but timing precision and operational efficiency deteriorate
Solution Approach 1:
The patent divides the single memory core into two operational modes: first mode for read operations and second mode for write operations. By segmenting the operational timeline and using mode selection signals, the system achieves sequential access patterns that preserve timing precision while maintaining area efficiency. The memory core is physically unified but operationally segmented through control logic.
Solution Approach 2:
The patent implements dynamic clocking where the write clock is generated based on the state of the read clock. When the read clock is active, the write clock is inhibited; when the read clock is inactive, the write clock becomes active. This dynamic clock generation adapts the timing characteristics to the current operational mode, ensuring proper timing margins are maintained while enabling flexible read-write sequencing.
2Device complexity
If pseudo dual port memory uses a single memory core for both read and write operations, then device complexity is reduced, but operational efficiency deteriorates
Solution Approach 1:
The patent employs periodic action by dividing the memory cycle into distinct phases: a first period for read operations and a second period for write operations. The mode selection signal periodically switches between modes, and the clock generation circuitry produces periodic clock pulses synchronized to the appropriate phase. This periodic structuring allows the single memory core to efficiently handle both read and write operations without interference, improving operational efficiency while maintaining low complexity.
3Reliability
If write clock is generated in response to read clock resetting, then timing synchronization is improved, but timing flexibility deteriorates
Solution Approach 1:
The patent implements feedback by using the read clock signal state as the trigger for write clock generation. The write clock generation circuit monitors the read clock and automatically generates write clock pulses at appropriate moments based on read clock activity. This feedback mechanism ensures automatic timing synchronization between read and write operations, preventing conflicts while maintaining reliability. The system adapts to different operational scenarios through this intelligent feedback-based clock generation.
Data Source
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AI summary
Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.