Pseudo Dual Port Memory Write Driver Speed
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Solution Overview
Problem
Pseudo dual port memories face speed limitations due to the cleanup time required for precharging and discharging bit lines, which increases write access time and limits operating frequency, while splitting into multiple banks to reduce capacitive load increases area and power overhead.
Innovation Solution
A write driver that selectively precharges only one bit line or its complement in a bit line pair based on the binary value to be written, reducing the cleanup time and eliminating the need for subsequent discharge, thereby allowing faster write operations and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional precharge and discharge operations are used for both bit lines in a bit line pair, then the bit lines are properly prepared for write operations, but the cleanup time increases write access time and limits operating frequency
Solution Approach 1:
The patent applies partial action by selectively precharging only one bit line in each bit line pair based on the write data value, rather than precharging both bit lines. This reduces the cleanup time and write access time, thereby improving operating frequency while maintaining proper write operation functionality
Solution Approach 2:
The patent uses preliminary action by determining the write data value in advance and selectively precharging the appropriate bit line before the write operation begins. This advance preparation eliminates the need for subsequent discharge operations, reducing cleanup time and improving speed
2Speed
If multiple memory banks are used to reduce capacitive load on bit lines, then bit lines can be charged and discharged more rapidly, but area and power overhead increases, negating the size advantage of PDP memories
Solution Approach 1:
The patent changes the operational parameters of the bit lines by selectively precharging only one bit line per pair based on write data. This parameter change reduces the effective capacitive load that must be charged during write operations, enabling faster write access times without requiring multiple memory banks, thus maintaining area efficiency while achieving speed improvements
Data Source
AI summary
A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.