Pseudo-Dynamic Interlock Circuit for Multi-Voltage Hold Timing
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Solution Overview
Problem
Large voltage offsets between different voltage domains in multi-voltage circuits cause hold time problems, leading to inefficiencies in signal evaluation and increased latency, as existing solutions like level shifters and synchronizers either slow down the circuit or significantly limit bandwidth.
Innovation Solution
An interlock circuit design that includes a keeper circuit and a pull-down circuit, allowing signals from different voltage domains to be combined without the need for a level shifter, ensuring hold timing is met across a wide voltage range without sacrificing setup time, using a pseudo-dynamic NAND structure with transistors that adjust based on input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level shifter is used to shift voltage of one signal so both signals are in the same voltage domain, then hold time problems are fixed, but the maximum frequency of the circuit is slowed down
Solution Approach 1:
The patent changes the voltage parameter directly at the output node by controlling the pull-up and pull-down circuits, eliminating the need for level shifters. The keeper circuit dynamically adjusts the voltage state based on input signals from different voltage domains, maintaining hold time without the frequency penalty of traditional level shifting approaches.
Solution Approach 2:
The patent extracts and removes the level shifter component from the circuit architecture. By implementing voltage control directly through the keeper circuit and pull-up/pull-down networks, the design eliminates the intermediate voltage conversion stage that was causing frequency degradation, while still solving the hold time problem.
2Reliability
If synchronizers are used to handle signals from different voltage domains, then hold time issues are resolved, but bandwidth and latency are significantly limited
Solution Approach 1:
The patent segments the voltage domain handling into separate pull-up and pull-down circuits that operate independently on the output node. This segmentation allows each circuit to be optimized for its specific voltage domain while working together to resolve timing issues, avoiding the need for multi-cycle synchronizer operations that limit bandwidth.
Solution Approach 2:
The patent implements a dynamic keeper circuit that actively responds to input signal transitions from different voltage domains. The circuit dynamically switches between holding high voltage state and allowing pull-down based on the timing and voltage levels of input signals, providing real-time hold time management without the fixed multi-cycle delay of traditional synchronizers.
3Stability of the object's composition
If the keeper circuit is made stronger to maintain output at high voltage level, then voltage stability is improved, but the output node cannot transition to low voltage level when needed
Solution Approach 1:
The patent introduces a pull-down circuit as a counterbalancing force to the keeper circuit's pull-up action. When both input signals are at their high voltage levels, the pull-down circuit activates to counteract the keeper circuit, enabling the output node to transition to a low voltage level. This counterweight mechanism maintains voltage stability during normal operation while enabling timely transitions when required.
Data Source
AI summary
An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.