Pseudo-Interleaved DAC Architecture for High-Speed Low-Power Sampling
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Solution Overview
Problem
Existing time-interleaving digital-to-analog converters (DACs) face challenges in maintaining low power consumption while achieving high sampling rates due to the need for narrow pulse width clock signals and high current consumption, which are difficult to generate and distribute efficiently.
Innovation Solution
A pseudo interleaved architecture for the DAC, utilizing N/2 slices with down and up switch circuitries, shares current sources between data flows, and uses complementary clocks with wider pulse widths to reduce total current consumption by 50% and eliminate the need for narrow pulse width signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional time-interleaving techniques are used to achieve high sampling rates, then the sampling rate increases, but the power consumption increases and narrow pulse width clock signals become difficult to generate and distribute
Solution Approach 1:
The patent divides the high-speed data stream into N/2 separate data flows, each processed by a dedicated DAC slice operating at a lower sampling rate (Fs/N). This segmentation allows each slice to use wider pulse width clock signals that are easier to generate and distribute, while collectively achieving the high sampling rate Fs through time-interleaved operation.
Solution Approach 2:
The patent merges N/2 DAC slices with shared current sources to achieve high sampling rate performance. By combining the outputs of multiple slices that share common current sources, the system achieves the equivalent performance of a single high-speed DAC while using fewer current sources and lower power consumption.
2Speed
If conventional time-interleaving techniques are used to achieve high sampling rates, then the sampling rate increases, but the current consumption increases
Solution Approach 1:
The patent makes current sources serve multiple functions by having each current source shared between two different data flows. A single current source is used alternately for two different DAC slices through time-interleaved operation, doubling the utilization efficiency of each current source and reducing the total number of current sources needed by 50%.
3Speed
If narrow pulse width clock signals are used to drive N slices of DAC, then high sampling rate is achieved, but the clock signals become difficult to generate and distribute
Solution Approach 1:
The patent changes the pulse width parameter of clock signals from narrow (difficult to generate and distribute) to wide (easy to generate and distribute). By using wider pulse width clock signals with frequency Fs/N instead of narrow pulse width signals at frequency Fs, the system achieves the same high sampling rate performance while dramatically improving clock signal generation and distribution ease.
Data Source
AI summary
A time-interleaved digital-to-analog converter for an optical transmitter includes a DAC core having a plurality of slices and current sources for converting complementary data signals to analog signals at output nodes of the DAC core, a down switch circuitry configured to connect, for each slice of the DAC core, a current from one of the current sources to a first data input path or a second data input path respectively corresponding to first complementary data signals and second complementary data signals supplied to the slice of the DAC core, an up switch circuitry configured to connect the current to the output nodes, and a data switch circuitry configured to, for each slice of the DAC core, selectively connect the current received via the down switch circuitry and either the first data input path or the second data input path.