Pseudo Layer Edge Recognition for Mixed Signal Layout Verification
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Solution Overview
Problem
Conventional schemes for applying voltage rules to semiconductor circuit designs do not adequately address the interfaces and edges of different areas, leading to inadequate testing and potential electrical isolation issues due to uniform voltage rule application.
Innovation Solution
The implementation of a pseudo layer mechanism that applies distinct voltage rules to area edges, with edges uncovered by the pseudo layer subjected to a first voltage rule and those covered by it validated using default or associated design rules, ensuring appropriate voltage rule application at interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform voltage rules are applied to all areas of a semiconductor circuit design, then the verification process is simple and consistent, but the edges and interfaces of different areas are not adequately tested, leading to potential electrical isolation issues
Solution Approach 1:
The patent segments the verification process by introducing a pseudo layer that distinguishes between area interiors and edges. The pseudo layer is placed only at area edges, allowing the verification tool to apply different voltage rules to edges versus interiors. This segmentation enables targeted verification of critical edge regions without complicating the entire verification system.
Solution Approach 2:
The patent implements local quality by applying different voltage rules to different spatial locations within the design layout. Specifically, edge regions (marked by the pseudo layer) receive one set of voltage rules, while interior regions receive another set. This localized approach ensures that critical edge interfaces receive appropriate verification without subjecting the entire design to overly complex rules.
2Reliability
If distinct voltage rules are applied to area edges to ensure adequate testing, then electrical isolation reliability is improved, but the verification process becomes more complex
Solution Approach 1:
The patent introduces a pseudo layer as an intermediary element that facilitates the application of distinct voltage rules to area edges. This pseudo layer acts as a mediator between the verification tool and the actual circuit layout, allowing the tool to identify and apply appropriate voltage rules to edge regions without requiring complex modifications to the underlying verification infrastructure.
Solution Approach 2:
The patent adds a new dimensional layer (the pseudo layer) to the traditional two-dimensional layout verification process. This pseudo layer exists as a separate verification construct that overlays the physical layout, enabling the verification tool to distinguish between edge and interior regions and apply corresponding voltage rules without altering the fundamental layout structure.
3Manufacturing precision
If conventional voltage rule software is used without edge recognition, then the verification process is straightforward, but edges of areas are tested under less than adequate voltage rules
Solution Approach 1:
The patent implements preliminary action by pre-placing the pseudo layer at area edges before the voltage rule verification process begins. This preparatory step ensures that when the verification tool executes, it can immediately identify edge regions and apply the appropriate voltage rules without requiring complex real-time analysis during verification.
Solution Approach 2:
The patent creates a verification copy of the layout that includes the pseudo layer, which is then used for voltage rule verification. This copied verification model allows the application of enhanced edge-aware voltage rules without modifying the original design layout, maintaining simplicity in the original design process while improving verification accuracy.
Data Source
AI summary
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.