Pseudo Lockstep Execution for Silent Data Corruption Detection
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Solution Overview
Problem
Existing CPU cores lack robust error detection mechanisms to identify Silent Data Corruption (SDC) errors, which can result from technology node shrinkage, unreliable transistors, and insufficient burn-in testing.
Innovation Solution
Implementing a pseudo-lockstep error detection mechanism where a primary core and a secondary core execute the same instruction segment, with a line eviction synchronizer ensuring cache line comparison for exact matches, thereby detecting errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error checking mechanisms are implemented in CPU cores, then detection capability for some errors is improved, but the mechanisms are not robust enough to detect SDC errors and may cause performance overhead
Solution Approach 1:
The patent uses a secondary core that copies the execution of the primary core to detect SDC errors. The secondary core executes the same instructions and data as the primary core, allowing comparison of results to identify silent data corruption without requiring complex checking mechanisms within each core
Solution Approach 2:
The patent introduces a result comparator as an intermediary component that compares the outputs of the primary and secondary cores. This mediator detects discrepancies indicating SDC errors without requiring complex error checking logic within the CPU cores themselves
2Reliability
If multiple cores execute the same instructions for error detection, then SDC detection capability is improved, but synchronization of cache lines becomes complex
Solution Approach 1:
The patent employs a line eviction synchronizer that uses feedback from cache line eviction events to coordinate between the primary and secondary cores. When the primary core evicts a cache line, the synchronizer triggers the secondary core to evict the corresponding cache line, ensuring synchronization without complex advance coordination
Solution Approach 2:
The patent establishes preliminary correspondence between cache lines of the primary and secondary cores before eviction. The eviction table pre-associates cache line indices from both cores, so when eviction occurs, the corresponding lines are already identified and can be compared immediately without complex runtime synchronization
3Reliability
If cores run in error detection mode continuously, then error detection reliability is improved, but productivity is reduced due to redundant execution
Solution Approach 1:
The patent implements partial error detection by using the secondary core only for executing instructions and comparing results, while relying on the primary core for actual productive work. The secondary core performs excessive execution of the same instructions purely for detection purposes, accepting the redundancy as necessary for SDC detection
Solution Approach 2:
The patent makes the secondary core multi-functional by using it both for error detection (comparing results with primary core) and for potential productive work. The same core infrastructure serves dual purposes: detecting SDC errors through result comparison and contributing to computational output when configured appropriately
Data Source
AI summary
The present disclosure provides for automatically detecting errors, such as SDC, in a multi-core computing environment. For example, cores may run in an error detection mode, in which multiple cores repeat the same execution of instructions and the results are compared. Based on the results, it may be determined whether one of the cores is failing.