Pseudo-Memory Interface for Modular SoC Adaptability
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Solution Overview
Problem
The existing design of system-on-a-chip (SOC) memory interfaces is not modular, leading to inefficiencies when adapting for applications with fewer memory channels, requiring significant redesign time and resources to remove unneeded channels and dependencies, thus prolonging the time to market for integrated circuits.
Innovation Solution
The introduction of a pseudo-memory channel physical interface, which is logically equivalent to the operative memory channel interface but operates with different voltage and timing characteristics, allowing for the reuse of existing designs by separating fully operational and pseudo-physical interfaces, reducing power consumption and area, and enabling faster integration into target applications with fewer channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a modular memory interface design is implemented, then adaptability to different applications is improved, but device complexity increases due to the need to manage multiple interface types (operative and pseudo)
Solution Approach 1:
The memory interface is segmented into multiple independent channels, each capable of being configured as either operative or pseudo. This segmentation allows selective activation of channels based on application requirements, enabling adaptability without requiring complete redesign of the interface architecture.
Solution Approach 2:
The memory interface is designed with universal channels that can serve multiple functions: operative channels for full functionality and pseudo channels for reduced functionality. This multi-functionality allows a single interface design to accommodate various applications with different channel requirements, from full-featured to power-constrained scenarios.
2Reliability
If all memory channels are made fully operative, then functionality is maximized, but power consumption and area increase
Solution Approach 1:
Different channels within the memory interface are assigned different qualities: some channels are configured as operative with full voltage and timing characteristics, while others are configured as pseudo with relaxed characteristics. This local differentiation allows the system to maximize functionality where needed while reducing power consumption and area where complete functionality is not required.
Solution Approach 2:
Instead of making all channels fully operative, the design allows partial action by configuring channels as pseudo-operational. This partial action approach provides sufficient functionality for power-constrained applications while avoiding the excessive power consumption and area that would result from making all channels fully operative.
3Adaptability or versatility
If existing designs are completely redesigned for each application, then adaptability is achieved, but time to market increases
Solution Approach 1:
The memory interface is pre-configured with multiple channels that can be selectively activated based on application requirements. This preliminary configuration allows the same base design to be quickly adapted to different applications without requiring complete redesign, significantly reducing time to market while maintaining adaptability.
Data Source
AI summary
A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.