Pseudo multi-port memory with memory cells each having two-port memory cell architecture and multiple enable pulses on same wordline and associated memory access method

The patent applies multi-functionality by enabling a single two-port memory cell to perform multiple read operations through time-multiplexed access. By using multiple enable pulses on the same wordline within one clock cycle, the memory cell serves as multiple functional ports (pseudo multi-port), achieving 4X read throughput without duplicating hardware resources. This resolves the contradiction by making one memory cell perform the work of four separate memory cells.

The patent employs periodic action through multiple enable pulses (e.g., four enable pulses) applied to the same wordline within a single clock cycle. Each pulse enables sequential access to the memory cell at different time intervals, creating a time-multiplexed multi-port effect. This periodic pulsing allows one memory cell to serve multiple read operations, achieving high throughput without increasing hardware complexity.

The patent applies preliminary action by pre-charging the bitlines and preparing the memory cell before each enable pulse arrives. The row decoder and sense amplifiers are pre-configured to handle the upcoming read operation, ensuring that when each enable pulse occurs, the memory cell is ready for immediate access. This preliminary preparation simplifies the timing control by establishing a predictable sequence of operations.

The patent segments the memory access operation into distinct time slots corresponding to each enable pulse. Each pulse handles a separate read operation independently, allowing the timing control to manage multiple accesses as discrete, manageable units rather than a complex continuous operation. This segmentation makes the timing control more tractable and implementable.

The patent applies dimensionality change by routing bitlines across multiple metal layers (e.g., first bitline on first metal layer, second bitline on second metal layer). This vertical stacking in the third dimension allows memory cells to be connected to multiple bitlines without increasing planar area, thereby improving density and access speed. The multi-layer approach resolves the contradiction by utilizing unused vertical space in the chip structure.

The patent implements nesting by placing memory cells at the same column position but connecting them to different bitlines on different metal layers. This nested arrangement allows multiple memory cells to occupy the same horizontal space while being electrically separated through vertical layering. The nested structure achieves high density without complicating the manufacturing process, as it uses standard multi-layer interconnect technology.