Pseudo NMOS Delay Line for Low-Jitter DLL Synchronization
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Solution Overview
Problem
Existing delay locked loop (DLL) circuits using CMOS transistors result in significant output signal jitter for high-frequency signals due to large delay amounts, affecting synchronization and resolution.
Innovation Solution
Implementing delay cells with Pseudo NMOS transistors, composed of a PMOS transistor and multiple NMOS transistors, which offer smaller delay amounts and lower input resistance, and using an enable signal to control the PMOS transistor's conductive state to minimize short current and adjust delay effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors are used to implement delay cells, then the circuit can achieve standard CMOS compatibility and manufacturing, but the delay amount becomes large causing output signal jitter in high-frequency signals
Solution Approach 1:
The patent changes the transistor type parameter from CMOS to Pseudo NMOS, which fundamentally alters the electrical characteristics including lower input resistance and smaller delay amount, directly resolving the contradiction between synchronization accuracy and delay time
Solution Approach 2:
The patent introduces an enable signal that dynamically controls the conductive state of the PMOS transistor, allowing the delay cell to be selectively activated or deactivated, providing dynamic control over the delay function while maintaining low delay characteristics
2Loss of time
If Pseudo NMOS transistors are used to reduce delay amount, then signal jitter is reduced and synchronization accuracy improves, but the circuit structure becomes more complex compared to standard CMOS
Solution Approach 1:
The Pseudo NMOS transistor is segmented into distinct PMOS and NMOS components with specific connectivity patterns, allowing the complex function to be achieved through modular transistor arrangement rather than a monolithic complex structure
Solution Approach 2:
The Pseudo NMOS transistor structure serves multiple functions: it provides the primary delay function, acts as a controllable switch through the enable signal, and maintains compatibility with standard CMOS manufacturing processes, reducing the need for additional specialized components
3Ease of operation
If the PMOS transistor is kept conductive to simplify control, then the delay cell operates continuously, but short current increases reducing efficiency
Solution Approach 1:
The enable signal implements periodic control of the PMOS transistor, switching it between conductive and non-conductive states in sync with the clock signal cycles, allowing the transistor to conduct only during necessary periods while remaining simple to control through a single enable input
Data Source
AI summary
A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.