Pseudo-Non-Volatile Memory Cells Eliminate DRAM Refresh Power
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Solution Overview
Problem
Conventional DRAM memory devices consume power during periods of inactivity due to refresh operations, which can be reduced but not eliminated, leading to ongoing power consumption.
Innovation Solution
Implementing pseudo-non-volatile memory cells with a 2T1C configuration where capacitors are not coupled to a cell plate power supply, allowing data retention without refresh operations, and disabling power to the memory array while other system components remain powered, entering a pseudo-non-volatile power state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM memory devices perform refresh operations during periods of inactivity, then data retention is maintained, but power consumption continues during idle periods
Solution Approach 1:
The patent changes the operational parameters of the memory device by entering a power-down state where the memory array is powered off during idle periods. This parameter change allows the device to eliminate refresh operations and associated power consumption while maintaining data retention capabilities through the ability to quickly power up and restore operations when needed.
2Use of energy by moving object
If power is completely eliminated from the memory array during inactivity, then power consumption is significantly reduced, but data retention capability is compromised
Solution Approach 1:
The patent applies preliminary action by ensuring data is written and stabilized in the memory array before transitioning to the power-down state. This preliminary data preparation ensures that when power is restored, the data is already in a retainable state, eliminating the need for continuous refresh operations while maintaining data integrity.
Solution Approach 2:
The patent treats the powered-on state as a temporary, disposable condition that is only maintained when absolutely necessary for data retention. By transitioning to a power-down state during idle periods, the system accepts that the memory array will be in a non-operational state temporarily, but this is acceptable because data can be restored or rewritten when power is reinstated, making the powered-on state a short-lived, resource-intensive condition that is minimized.
3Loss of energy
If the memory array is powered down during inactivity, then energy efficiency is enhanced, but the memory device cannot immediately respond to access requests
Solution Approach 1:
The patent implements periodic action by alternating between powered-on and powered-off states based on activity detection. The system monitors for idle conditions and transitions to power-down mode, then periodically powers up when access requests are detected. This periodic cycling optimizes energy efficiency while maintaining acceptable response times by ensuring the system is powered when needed and saved when idle.
Data Source
AI summary
An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.