Pseudo-Orthogonal Code Generator Without ROM-Based Logic
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Solution Overview
Problem
Conventional orthogonal code generators have low spectral efficiency and complex configurations, leading to slower operating speeds and increased gate area when implemented as ASICs, due to their reliance on ROMs and multiple multiplexers and adders.
Innovation Solution
A pseudo-orthogonal code generator is designed with a serial-to-parallel converter, a 4-bit counter, and a combined circuit unit that generates 16-bit pseudo-orthogonal codes using 9-bit parallel data and counter values, reducing complexity and size by eliminating the need for ROMs and simplifying the circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional orthogonal code generator uses ROM and multiple multiplexers and adders, then the spectral efficiency can be improved, but the device complexity and gate area increase significantly
Solution Approach 1:
The patent extracts and eliminates the ROM component from the code generator system. Instead of storing pre-computed orthogonal codes in a 512×16-bit ROM, the invention generates pseudo-orthogonal codes on-the-fly using a simplified circuit with a serial-to-parallel converter, counter, and logic operations, thereby reducing device complexity while maintaining spectral efficiency
Solution Approach 2:
The patent merges the functions of multiple components (serial-to-parallel converter, counter, and logic circuitry) into a unified pseudo-orthogonal code generator that produces codes directly without requiring separate ROM, multiplexer, and adder modules. This integration reduces the overall configuration complexity and gate area
2Measurement precision
If a pseudo-orthogonal code generator uses ROM for code storage, then the code generation accuracy is maintained, but the operating speed decreases
Solution Approach 1:
The patent replaces the mechanical/electronic ROM-based code retrieval system with a direct logic-based generation system. Instead of reading pre-stored codes from ROM memory, the invention uses real-time logic operations (XOR, AND, OR) on parallel data bits to generate pseudo-orthogonal codes, eliminating memory access delays and improving operating speed while maintaining code accuracy
3Adaptability or versatility
If the code generator uses a 512×16-bit ROM, then comprehensive code coverage is achieved, but the gate area and overall size become much larger
Solution Approach 1:
The patent creates a functional copy of the code generation capability without requiring physical storage of all possible codes. Instead of storing 512 different 16-bit codes in ROM, the invention uses a compact logic circuit that can generate the required pseudo-orthogonal codes on-demand through logical operations on input data, achieving comprehensive code coverage with minimal gate area
Solution Approach 2:
The patent transitions from a two-dimensional storage approach (ROM with 512 rows and 16 columns) to a computational approach where codes are generated through logical operations. This dimensionality change from storage to computation dramatically reduces the physical space required while maintaining the ability to produce comprehensive code sets
Data Source
AI summary
A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area.