Pseudo PN Junction for Selective Memory Block Erasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in selectively erasing multiple erase blocks coupled to the same string, particularly due to inefficiencies in generating gate-induced drain leakage (GIDL) holes, especially on the source side, which is harder to control and less effective.
Innovation Solution
The solution involves creating a pseudo PN junction adjacent to the selected erase block and supplying GIDL holes from this junction, rather than generating them at the ends of the strings. This is achieved by inducing a carrier concentration gradient using bias voltages, allowing for more precise and selective erasing of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GIDL holes are generated at the ends of the strings for erasing memory blocks, then the erase operation can be performed, but it is harder to control and less effective on the source side
Solution Approach 1:
The patent introduces a pseudo PN junction as an intermediary structure between the source and the selected erase block. This junction acts as a controlled interface that generates GIDL holes locally at the desired location, rather than relying on hole generation at the distant source end of the string. The pseudo PN junction mediates the erase process by providing a controllable hole generation point that improves both precision and effectiveness.
Solution Approach 2:
The patent applies local quality by creating a pseudo PN junction specifically at the boundary between unselected and selected erase blocks. This localized structure provides different properties (controlled hole generation) exactly where needed, rather than attempting to control GIDL generation uniformly across the entire string. The local modification enables precise control over which blocks are erased without affecting others.
2Reliability
If GIDL holes flow through unselected erase blocks to reach the selected block, then erasing can be achieved, but the reliability and performance of unselected memory cells are compromised
Solution Approach 1:
The patent extracts the GIDL hole generation process from the source end and relocates it to the pseudo PN junction adjacent to the selected erase block. By taking out the hole generation from the common source region and placing it locally at the junction, the erase operation can proceed without requiring holes to flow through unselected blocks, thus protecting their integrity while maintaining erase efficiency.
Solution Approach 2:
The patent changes the spatial parameter of GIDL hole generation from the source end to the pseudo PN junction location. This parameter change in the generation position eliminates the need for holes to traverse through unselected blocks, thereby preserving their reliability while achieving the desired erase effect in the selected block.
3Quantity of substance
If multiple erase blocks are coupled to the same string, then memory density is improved, but selective erasing becomes more difficult
Solution Approach 1:
The patent applies local quality by introducing a pseudo PN junction specifically at the boundary of the selected erase block. This localized structure enables precise control over hole generation at the exact location needed for selective erasing, allowing multiple blocks on the same string to be differentiated and erased independently without affecting adjacent unselected blocks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more selective and precise erasing of memory cells without compromising the reliability and performance of unselected memory cells, as it avoids the need for GIDL holes to flow through unselected erase blocks.
Implementation Method 1
gate-induced drain leakage (GIDL) holes
Implementation Method 2
inducing a carrier concentration gradient using bias voltages
Data Source
AI summary
Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.