Pseudo-random Circuit Re-arranger for PCB Breach Detection
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Solution Overview
Problem
Existing technologies face difficulties in efficiently generating multiple intertwined pseudo-random or random circuits that cover a predetermined area, making it challenging to detect and respond to breaches or shorts effectively.
Innovation Solution
A method and system that rearrange pseudo-random or random circuits by forming a grid of macro nodes with micro nodes, identifying candidate macro nodes with parallel segments, and reconfiguring them to create non-parallel segments, allowing for the detection of shorts or breaches and enabling actions such as halting power to the item.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple intertwined pseudo-random circuits are generated, then the ability to detect breaches and shorts is improved, but the complexity of generating and managing these circuits increases
Solution Approach 1:
The patent segments the circuit generation process into discrete macro nodes containing micro nodes, allowing systematic manipulation of circuit paths. Each macro node can be independently processed to create parallel segments that are later re-arranged into non-parallel configurations, enabling multiple intertwined circuits to be generated through structured segmentation rather than random generation.
Solution Approach 2:
The patent transforms 2D parallel circuit path segments into 3D non-parallel configurations by re-arranging micro node segments within macro nodes. This dimensional transformation creates intertwined circuit paths that occupy different spatial dimensions, increasing breach detection capability while maintaining manageable complexity through systematic re-arrangement operations.
2Shape
If parallel circuit path segments are re-arranged to non-parallel segments, then the intertwining of multiple circuits is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-defining macro nodes with specific micro node configurations and parallel segments before final circuit generation. These pre-structured elements can be systematically re-arranged into non-parallel configurations using automated algorithms, reducing manufacturing complexity compared to creating intertwined circuits from scratch.
Solution Approach 2:
The patent changes geometric parameters of circuit paths by transforming parallel segments into non-parallel configurations through controlled re-arrangement of micro nodes within macro nodes. This parameter transformation maintains electrical functionality while creating the desired intertwined shape, balancing manufacturing ease with circuit complexity requirements.
Data Source
AI summary
A method comprises forming a grid provided with a plurality of macro nodes. The grid comprises a plurality of meandering electrically conductive circuit paths through the plurality of macro nodes. The method comprises identifying a candidate macro node in the grid which includes only parallel micro node segments and selecting the candidate macro node. The method includes re-arranging the parallel micro node segments of the plurality of micro node meandering electrically conductive circuit paths in the candidate macro node of the grid such that at least one micro node segment is changed electrically to a non-parallel micro node segment in relation to other micro node segments in the candidate macro node to generate data representative of re-arranged meandering electrically conductive circuit paths for the grid. The method includes forming the re-arranged meandering electrically conductive circuit paths for the grid. A computing device and a computer program product for performing the method are also provided.