Pseudo-Random Clock Signal Generation for Side-Channel Attack Mitigation
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Solution Overview
Problem
Current security measures are inadequate in preventing side-channel attacks like differential power analysis (DPA) and simple power analysis (SPA), which exploit the regularity of power consumption in digital circuits to extract sensitive information, such as encryption keys.
Innovation Solution
The implementation of a system and method that randomizes the clock signal using a linear feedback shift register (LFSR) to generate a pseudo-random clock pattern, ensuring that power events do not occur at the same time, thereby complicating the collection and analysis of power signatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a regular clock signal is used to initiate power events in the circuit, then the circuit operates with predictable timing and standard digital library elements, but power events occur at the same time enabling attackers to collect and analyze power signatures for side-channel attacks
Solution Approach 1:
The patent applies dynamics by transforming the static, periodic clock signal into a dynamic, pseudo-random clock pattern. The LFSR continuously generates varying clock intervals, making the timing of power events unpredictable. This dynamic approach ensures that identical operations do not occur at the same time, thereby preventing attackers from collecting synchronized power signatures for DPA and SPA attacks.
Solution Approach 2:
The patent changes the temporal parameters of the clock signal by using an LFSR to generate pseudo-random sequences that vary the clock interval. Instead of a fixed period, the clock signal's timing parameters are continuously changed according to the LFSR output, making power event timing unpredictable while maintaining circuit operation.
2Reliability
If additional circuitry or analog delays are used to randomize the clock signal, then power event timing becomes unpredictable, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent replaces analog delay mechanisms with a digital LFSR-based clock generation system. Instead of using analog components that would complicate manufacturing and reduce precision, the invention uses digital logic elements (flip-flops, XOR gates) to generate pseudo-random clock patterns, maintaining ease of manufacture with standard digital ASIC and FPGA library elements.
Solution Approach 2:
The LFSR circuit is self-contained and generates its own pseudo-random sequence without requiring external analog components or additional circuitry. The system uses its internal state and feedback mechanisms to produce the randomized clock pattern, eliminating the need for external randomization hardware and simplifying manufacturing.
3Reliability
If the clock signal regularity is modified to prevent power analysis attacks, then power events no longer occur at predictable times, but the ability to use standard digital ASIC and FPGA library elements and design tools is compromised
Solution Approach 1:
The patent achieves universality by designing the LFSR-based clock generation system using standard digital logic components that are universally supported by ASIC and FPGA design tools. The pseudo-random clock pattern generator can be implemented using common library elements, maintaining compatibility with standard design flows while providing the security function of randomizing power event timing.
Data Source
AI summary
A system and method to mitigate or complicate the use of differential power analysis (DPA) and simple power analysis (SPA) in the attack of a targeted integrated circuit, or device containing an integrated circuit, that is processing sensitive information. The system and method modifies the regularity of a clock that initiates the power events within the circuit such that subsequent processing of information does not always occur at the same time.