Pseudo-Random Signal Tamper Detection Integrated Circuit

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Solution Overview

Problem

Existing tamper detection systems in electronic devices are not tamper-proof and can be compromised, as they rely on physical barriers that may be overcome or bypassed, lacking effective digital continuity monitoring.

Innovation Solution

An integrated circuit with signal generator and comparator circuitry that generates a pseudo-random digital signal and compares input signals to detect tampering, using Boolean logic and delay mechanisms to provide a tamper detection signal, which triggers corrective actions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If physical barriers or enclosures are used to prevent unauthorized access, then device security is improved, but these methods are not tamper-proof and can be compromised

Engineering Contradiction:
Improvetamper detection reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces physical barrier mechanisms with a digital signal-based tamper detection system. Instead of relying solely on mechanical enclosures, the system uses pseudo-random digital signals transmitted through conductive paths to detect tampering digitally, substituting mechanical security with electronic verification methods.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system creates a digital copy of the expected signal behavior by generating pseudo-random sequences at both the transmitter and receiver ends. By comparing the received signal against the locally generated copy, the system can verify integrity without adding complex external verification hardware.

Inventive Principle:
Principle #26Copying

2Reliability

If digital continuity monitoring is implemented, then tamper detection capability is improved, but the system complexity increases

Engineering Contradiction:
Improvedigital continuity monitoringVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The tamper detection system is integrated into existing communication circuits, allowing the same conductive paths and signal processing circuits to serve both data communication and security monitoring functions. This multi-functionality approach avoids adding separate dedicated security hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses its own communication infrastructure to perform tamper detection. The pseudo-random signal is generated, transmitted, and verified using the existing circuitry, making the security system self-contained and eliminating the need for external monitoring equipment.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If pseudo-random digital signal comparison is used, then tamper detection accuracy is improved, but signal processing complexity increases

Engineering Contradiction:
Improvetamper detection accuracyVSAvoidsignal processing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system changes the temporal parameters of the signal by introducing controlled delays to the pseudo-random sequence. By comparing the delayed local signal with the received signal, the system achieves accurate tamper detection while managing complexity through parameter adjustment rather than complex processing algorithms.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The pseudo-random signal is generated and compared in periodic cycles, allowing the system to continuously monitor for tampering events. This periodic operation simplifies the processing requirements compared to continuous analysis, as the system only needs to perform comparison operations at discrete time intervals.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11599684B2System and method of digital continuity tamper detection
Publication Date: 2023.03.07 SILICON LABORATORIES INC
  • US11599684B2 patent drawing
  • US11599684B2 patent drawing
  • US11599684B2 patent drawing

AI summary

An integrated circuit including an input terminal and an output terminal, signal generator circuitry that generates a pseudo-random digital signal provided at the output terminal, and comparator circuitry that compares an input signal received via the input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof. The signal generator circuitry may be a pseudo-random binary sequence generator or may be a linear-feedback shift register with software triggered reloading. The comparator circuitry may include a Boolean logic exclusive-OR gate for comparing the output and input signals. A method of detecting tampering including generating and providing a pseudo-random digital signal at an output terminal and comparing an input signal received via an input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof.