Pseudo-Return-to-Zero DAC Calibration for CT Sigma-Delta Linearity
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Solution Overview
Problem
Continuous-time sigma-delta analog-to-digital converters face challenges in achieving high linearity and precision due to inter-symbol interference and mismatches between digital-to-analog converter (DAC) units caused by process variations, which affect the accuracy of analog-to-digital conversions.
Innovation Solution
The implementation of a dual DAC unit circuit with pseudo-return-to-zero operations and complementary MOS transistors reduces inter-symbol interference, and a calibration scheme that utilizes the return-to-zero time interval for background calibration of an array of DAC circuits to ensure high linearity and precision, particularly in continuous-time sigma-delta analog-to-digital converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single DAC unit is used in continuous-time sigma-delta ADC, then the circuit structure is simple, but inter-symbol interference occurs and linearity deteriorates due to process variations
Solution Approach 1:
The patent divides a single DAC unit into multiple parallel DAC units (e.g., two or more). Each DAC unit processes a portion of the digital input signal and contributes to the overall analog output. This segmentation reduces inter-symbol interference within each individual DAC unit and provides redundancy to compensate for process variations, thereby improving linearity while distributing the functional load across multiple simpler units.
Solution Approach 2:
The patent introduces calibration mechanisms that dynamically adjust parameters of the DAC units (such as timing parameters, current parameters, or voltage parameters) to compensate for process variations. By changing these parameters through calibration circuits and control logic, the system maintains high linearity despite manufacturing tolerances and environmental conditions.
2Reliability
If multiple DAC units are used to reduce inter-symbol interference, then linearity improves, but mismatches between DAC units due to process variations increase
Solution Approach 1:
The patent incorporates calibration circuits that measure the actual performance of each DAC unit and generate feedback control signals. These feedback signals adjust the operating parameters of each DAC unit to compensate for mismatches caused by process variations. The calibration process continuously monitors and corrects deviations, ensuring that all DAC units operate with matched characteristics despite manufacturing tolerances.
Solution Approach 2:
The patent performs calibration operations during idle periods or return-to-zero intervals before the DAC units are needed for normal conversion. By preliminarily adjusting the parameters of each DAC unit during these intervals, the system prepares the units to operate with matched characteristics before processing actual signal data, thereby preventing mismatch-related errors during critical conversion operations.
3Measurement precision
If calibration operations are performed during active conversion, then DAC precision improves, but conversion time increases
Solution Approach 1:
The patent implements calibration operations periodically during return-to-zero intervals or idle periods between active conversion cycles. During normal conversion operations, the DAC units operate without calibration interference. The calibration process is activated periodically when the system can tolerate brief interruptions or when using redundant DAC units that allow calibration of one unit while another handles conversion. This periodic approach maintains precision without continuously extending conversion time.
Solution Approach 2:
The patent designs the calibration mechanism to operate during return-to-zero intervals, which are necessary periods where no actual signal conversion is occurring. By utilizing these otherwise wasted time intervals for calibration, the system maintains continuous useful action - the DAC units are either converting signals or being calibrated, with no idle time lost. This ensures conversion accuracy improves without extending the overall conversion time for active signal processing.
Data Source
AI summary
In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-ΣΔ) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.