Pseudo SCR ESD Protection Device With Floating N-Type Region
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Solution Overview
Problem
Existing ESD protection circuits with silicon-controlled rectifiers (SCRs) are prone to latch-up due to noise and leakage currents, which can damage internal circuits, and the holding voltage is not sufficient to prevent incorrect triggering during normal operations.
Innovation Solution
The ESD protection device features a pseudo SCR structure with a floating N-type doped region, increasing the holding voltage by isolating the N-type second doped region from conductive layers and forming a discharging path through a PNPN structure, thereby preventing latch-up during normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode string is added to increase holding voltage, then latch-up resistance is improved, but the device complexity and silicon area increase
Solution Approach 1:
The third N-type doped region serves multiple functions: it provides a conduction path during normal operation, prevents false latch-up during normal voltage conditions, and does not interfere with the ESD discharging path when activated. This multi-functional element increases latch-up resistance without requiring separate dedicated components, thus avoiding increased device complexity.
Solution Approach 2:
The patent merges the normal operation conduction function and the ESD protection function into a single integrated SCR structure with an additional doped region. Instead of adding separate diode strings or protection circuits, the solution combines multiple functions within the existing SCR architecture, maintaining simplicity while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the holding voltage of the ESD protection device, preventing incorrect triggering and protecting internal circuits from noise-induced damage, while maintaining a similar trigger voltage to the original SCR design.
Implementation Method 1
When an ESD event occurs, the ESD current can be discharged through the discharging path, so that an internal circuit connected between the high power node 24 and the low power node 26 can be protected
Implementation Method 2
The trigger voltage Vt of the SCR device 10 is approximately equal to the breakdown voltage of the P-N junction between the N-type well 14 and the p-type substrate 12, about 30-40 volts
Data Source
AI summary
The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.