Pseudo-shielded Capacitor Asymmetric Electrodes Parasitic Interference
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Solution Overview
Problem
As electronic devices miniaturize, parasitic capacitances between capacitors and grounded shielding structures become significant, leading to performance issues such as malfunction and interference, particularly in filtering and impedance matching applications, due to the close proximity of these components.
Innovation Solution
The design of capacitors with asymmetrically arranged electrodes and terminations, where the ground terminal is closer to the shielding structure than the signal terminal, and the use of multilayer ceramic capacitor methods to create pseudo-shielded capacitors that reduce parasitic interferences by maintaining a specified distance between electrodes and the capacitor's top wall, thereby minimizing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the dimension of consumer products is reduced, then the size of electronic devices is improved, but the spacing between capacitors and shielding structures decreases, leading to increased parasitic capacitances
Solution Approach 1:
The capacitor is designed with asymmetric electrode arrangements where the first electrode extends closer to the shielding structure than the second electrode. This asymmetric geometry creates unequal parasitic capacitances, with the closer first electrode forming a larger parasitic capacitance to ground that is intentionally designed to compensate for the performance degradation caused by the compact spacing to the shielding structure.
Solution Approach 2:
The patent modifies the physical parameters of the capacitor by adjusting the positions and extensions of the first and second electrodes relative to each other and to the shielding structure. By changing the geometric parameters (electrode lengths, positions, and orientations), the parasitic capacitance values are controlled to achieve desired performance in compact device configurations.
2Length of moving object
If the spacing between capacitor and shielding structure is reduced, then device compactness is improved, but performance degradation occurs due to parasitic interferences
Solution Approach 1:
The asymmetric electrode configuration creates a deliberate imbalance in parasitic capacitance distribution. The first electrode, being closer to the shielding structure, forms a larger parasitic capacitance to ground that is designed to offset the performance degradation from reduced spacing, while the second electrode maintains sufficient distance to minimize its parasitic effects.
Solution Approach 2:
Different regions of the capacitor are designed with different qualities - the first electrode region is optimized for being closer to the shielding structure with extended geometry to create beneficial parasitic capacitance, while the second electrode region is positioned farther away with different geometry to minimize harmful parasitic effects, creating local optimization throughout the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces parasitic capacitances, ensuring reliable performance and preventing unwanted interference between capacitors and shielding structures, allowing for more compact electronic device designs.
Implementation Method 1
The first electrode may be closer to a shielding structure than the second electrode. The unequal positions of the first and second electrodes may create unequal parasitic capacitances, such that the larger parasitic capacitance may compensate for performance degradation
Data Source
AI summary
Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.