Pseudo-SOI DRAM Transistors with Surrounding Gates
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges in achieving high integration levels while minimizing leakage and refresh rates, as increased integration leads to increased leakage, necessitating faster refresh rates, which is inefficient and drains battery power.
Innovation Solution
The development of DRAM constructions using pseudo-SOI technology to isolate source/drain regions from bulk semiconductor material and surround access transistors' channel regions with conductive gate material, reducing junction leakage and enabling lower refresh rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If increased channel doping is applied to alleviate short channel effects, then transistor performance is improved, but junction leakage increases
Solution Approach 1:
An intermediary layer of electrically insulating material is introduced between the source/drain regions and the bulk semiconductor material. This insulating layer acts as a mediator that prevents direct electrical contact, thereby reducing junction leakage while allowing the doped source/drain regions to maintain their function in controlling the channel.
Solution Approach 2:
The semiconductor structure is segmented into distinct regions: doped source/drain regions, an insulating intermediate layer, and bulk semiconductor material. This segmentation electrically isolates the doped regions from the bulk, preventing leakage currents while preserving the necessary transistor functionality.
2Productivity
If increased integration is achieved to decrease device size, then memory density is improved, but leakage increases requiring faster refresh rates
Solution Approach 1:
The insulating material layer serves as an intermediary that electrically isolates the source/drain regions from the bulk semiconductor, thereby reducing leakage currents. This allows for increased integration and smaller device size without the penalty of increased leakage that would otherwise require faster refresh rates.
Solution Approach 2:
The solution introduces a vertical dimension to the problem by stacking layers (doped source/drain region, insulating material, bulk semiconductor) rather than relying solely on lateral scaling. This vertical segmentation enables higher integration while maintaining low leakage through the insulating barrier.
3Reliability
If faster refresh rates are implemented to compensate for increased leakage, then data retention is maintained, but power consumption increases
Solution Approach 1:
By introducing the insulating material as an intermediary layer, the structure reduces junction leakage at its source. This eliminates the need for frequent refresh operations, thereby maintaining data retention reliability while significantly reducing the power consumption associated with high-speed refreshing.
Solution Approach 2:
The insulating layer converts the potentially harmful effect of doped source/drain regions (which can cause leakage) into a beneficial structure by electrically isolating them from the bulk. This transformation allows the doped regions to be used without suffering from their usual leakage penalty, reducing refresh requirements and power consumption.
Data Source
AI summary
The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.